Improving the computing efficiency of HPC systems using a combination of proactive and preventive checkpointing

Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium, IPDPS 2013

Volumn , Issue , 2013, Pages 501-512

  Bouguerra, Mohamed Slim ^a   Gainaru, Ana ^a   Gomez, Leonardo Bautista ^b   Cappello, Franck ^a   Matsuoka, Satoshi ^b   Maruyam, Naoya ^c  

^a INRIA UIUC Joint Laboratory for Petascale Computing   (United States)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

^c RIKEN   (Japan)

Author keywords

Failure prediction; large scale HPC systems; multilevel checkpointing; resilience

Indexed keywords

DISCRETE-EVENT SIMULATORS; FAILURE PREDICTION; MEAN TIME BETWEEN FAILURES; MODEL-BASED SIMULATIONS; MULTILEVEL CHECKPOINTING; PARALLEL APPLICATION; PREDICTION PRECISION; RESILIENCE;

ALGORITHMS; DISTRIBUTED PARAMETER NETWORKS; MATHEMATICAL MODELS; SUPERCOMPUTERS;

EFFICIENCY;

EID: 84884837861     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2013.74     Document Type: Conference Paper

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