A roofline model of energy

Proceedings - IEEE 27th International Parallel and Distributed Processing Symposium, IPDPS 2013

Volumn , Issue , 2013, Pages 661-672

  Choi, Jee Whan ^a   Bedard, Daniel ^b   Fowler, Robert ^b   Vuduc, Richard ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Renaissance Computing Institute   (United States)

Author keywords

computational intensity; machine balance; performance analysis; power and energy modeling; roofline model

Indexed keywords

ALGORITHM PROPERTIES; COMPUTATIONAL INTENSITY; COST PARAMETERS; ENERGY MODEL; ENERGY-BASED; PERFORMANCE ANALYSIS; POWER MANAGEMENTS; ROOFLINE MODELS;

ALGORITHMS; DISTRIBUTED PARAMETER NETWORKS;

MATHEMATICAL MODELS;

EID: 84884824369     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2013.77     Document Type: Conference Paper

References (52)

1. K. Czechowski, C. Battaglino, C. McClanahan, A. Chandramowlishwaran, and R. Vuduc, "Balance principles for algorithm-architecture co-design," in Proc. USENIX Wkshp. Hot Topics in Parallelism (HotPar), Berkeley, CA, USA, May 2011.
2. R. Vuduc and K. Czechowski, "What GPU computing means for high-end systems," IEEE Micro, vol. 31, no. 4, pp. 74-78, July/August 2011.
3. K. Czechowski, C. McClanahan, C. Battaglino, K. Iyer, P.-K. Yeung, and R. Vuduc, "On the communication complexity of 3D FFTs and its implications for exascale," in Proc. ACM Int'l. Conf. Supercomputing (ICS), San Servolo Island, Venice, Italy, June 2012.
4. M. D. Hill and M. R. Marty, "Amdahl's Law in the Multicore Era," Computer, vol. 41, no. 7, pp. 33-38, Jul. 2008.
5. D. H. Woo and H.-H. S. Lee, "Extending Amdahl's Law for energy-efficient computing in the many-core era," IEEE Computer, vol. 41, no. 12, pp. 24-31, Dec. 2008.
6. T. Zidenberg, I. Keslassy, and U. Weiser, "Multi-Amdahl: How Should I Divide My Heterogeneous Chip?" IEEE Computer Architecture Letters, pp. 1-4, 2012.
7. H. T. Kung, "Memory requirements for balanced computer architectures," in Proceedings of the ACM Int'l. Symp. Computer Architecture (ISCA), Tokyo, Japan, 1986.
8. W. D. Hillis, "Balancing a Design," IEEE Spectrum, 1987.
9. R. W. Hockney and I. J. Curington, "f1/2: A parameter to characterize memory and communication bottlenecks," Parallel Computing, vol. 10, no. 3, pp. 277-286, May 1989.
10. G. E. Blelloch, B. M. Maggs, and G. L. Miller, "The hidden cost of low bandwidth communication," in Developing a Computer Science Agenda for High-Performance Computing, U. Vishkin, Ed. New York, NY, USA: ACM, 1994, pp. 22-25.
11. J. McCalpin, "Memory Bandwidth and Machine Balance in High Performance Computers," IEEE Technical Committee on Computer Architecture (TCCA) Newsletter, Dec. 1995.
12. S. Williams, A. Waterman, and D. Patterson, "Roofline: An insightful visual performance model for multicore architectures," Communications of the ACM, vol. 52, no. 4, p. 65, Apr. 2009.
13. H. Jia-Wei and H. T. Kung, "I/O complexity: The red-blue pebble game," in Proceedings of the thirteenth annual ACM symposium on Theory of computing - STOC '81. New York, New York, USA: ACM Press, May 1981, pp. 326-333.
14. S. W. Keckler, W. J. Dally, B. Khailany, M. Garland, and D. Glasco, "GPUs and the Future of Parallel Computing," IEEE Micro, vol. 31, no. 5, pp. 7-17, Sep. 2011.
15. M. A. Awan and S. M. Petters, "Enhanced Race-To-Halt: A Leakage-Aware Energy Management Approach for Dynamic Priority Systems," in 2011 23rd Euromicro Conference on Real-Time Systems. IEEE, Jul. 2011, pp. 92-101.
16. D. Bedard, M. Y. Lim, R. Fowler, and A. Porterfield, "PowerMon 2: Fine-grained, integrated measurement," RENaissance Computing Institute, University of North Caroliina, Chapel Hill, NC, USA, Tech. Rep., 2009.
17. L. GREENGARD and V. ROKHLIN, "A fast algorithm for particle simulations," Journal of Computational Physics, vol. 73, no. 2, pp. 325-348, Dec. 1987.
18. A. Chandramowlishwaran, J. W. Choi, K. Madduri, and R. Vuduc, "Towards a communication optimal fast multipole method and its implications for exascale," in Proc. ACM Symp. Parallel Algorithms and Architectures (SPAA), Pittsburgh, PA, USA, June 2012, brief announcement.
19. NVIDIA, "Compute Visual Profiler," 2012.
20. S. Kaxiras and M. Martonosi, Computer Architecture Techniques for Power-Efficiency, 1st ed. Morgan and Claypool Publishers, 2008.
21. J. Demmel, A. Gearhart, O. Schwartz, and B. Lipschitz, "Perfect strong scaling using no additional energy," University of California, Berkeley, CA, USA, Tech. Rep., 2012.
22. A. Tyagi, "Energy-Time Trade-offs in VLSI Computations," in Foundations of Software Technology and Theoretical Computer Science, vol. LNCS 405, 1989, pp. 301-311.
23. A. J. Martin, "Towards an energy complexity of computation," Information Processing Letters, vol. 77, no. 2-4, pp. 181-187, Feb. 2001.
24. R. Jain, D. Molnar, and Z. Ramzan, "Towards a model of energy complexity for algorithms," in IEEE Wireless Communications and Networking Conference, 2005. IEEE, 2005, pp. 1884-1890.
25. B. D. Bingham and M. R. Greenstreet, "Computation with Energy-Time Trade-Offs: Models, Algorithms and Lower-Bounds," 2008 IEEE International Symposium on Parallel and Distributed Processing with Applications, pp. 143-152, Dec. 2008.
26. V. A. Korthikanti and G. Agha, "Analysis of Parallel Algorithms for Energy Conservation in Scalable Multicore Architectures," in 2009 International Conference on Parallel Processing. Vienna, Austria: IEEE, Sep. 2009, pp. 212-219.
27. G. Aupy, A. Benoit, and Y. Robert, "Energy-aware scheduling under reliability and makespan constraints," INRIA, Grenoble, France, Tech. Rep. October, 2011.
28. R. Ge, X. Feng, and K. W. Cameron, "Performance-constrained distributed dvs scheduling for scientific applications on power-aware clusters," in Proceedings of the 2005 ACM/IEEE conference on Supercomputing, ser. SC '05. Washington, DC, USA: IEEE Computer Society, 2005, pp. 34-.
29. V. W. Freeh, D. K. Lowenthal, F. Pan, N. Kappiah, R. Springer, B. L. Rountree, and M. E. Femal, "Analyzing the energy-time trade-off in high-performance computing applications," IEEE Trans. Parallel Distrib. Syst., vol. 18, no. 6, pp. 835-848, Jun. 2007. (Pubitemid 46767744)
30. Y. Jiao, H. Lin, P. Balaji, and W. Feng, "Power and performance characterization of computational kernels on the gpu," in Green Computing and Communications (GreenCom), 2010 IEEE/ACM Int'l Conference on Int'l Conference on Cyber, Physical and Social Computing (CPSCom), dec. 2010, pp. 221-228.
31. R. Ge and K. Cameron, "Power-aware speedup," in In Proceedings of the 21st IEEE International Parallel and Distributed Processing Symposium (IPDPS 07), 2007.
32. S. Song, M. Grove, and K. W. Cameron, "An iso-energy-efficient approach to scalable system power-performance optimization," in Proceedings of the 2011 IEEE International Conference on Cluster Computing, ser. CLUSTER '11. Washington, DC, USA: IEEE Computer Society, 2011, pp. 262-271.
33. J. Dongarra, H. Ltaief, P. Luszczek, and V. M. Weaver, "Energy footprint of advanced dense numerical linear algebra using tile algorithms on multicore architecture," in The 2nd International Conference on Cloud and Green Computing, Nov. 2012.
34. X. Feng, R. Ge, and K. Cameron, "Power and energy profiling of scientific applications on distributed systems," in Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS), april 2005, p. 34.
35. G. Bosilca, H. Ltaief, and J. Dongarra, "Power profiling of Cholesky and QR factorizations on distributed memory systems," Computer Science - Research and Development, pp. 1-9, 2012.
36. R. Ge, X. Feng, S. Song, H.-C. Chang, D. Li, and K. Cameron, "Powerpack: Energy profiling and analysis of high-performance systems and applications," IEEE Transactions on Parallel and Distributed Systems (TPDS), vol. 21, no. 5, pp. 658-671, May 2010.
37. H. Ltaief, P. Luszczek, and J. Dongarra, "Profiling high performance dense linear algebra algorithms on multicore architectures for power and energy efficiency," Computer Science - Research and Development, pp. 1-11, 10.1007/s00450-011-0191-z.
38. H. Esmaeilzadeh, T. Cao, X. Yang, S. M. Blackburn, and K. S. McKinley, "Looking back and looking forward: power, performance, and upheaval," Commun. ACM, vol. 55, no. 7, pp. 105-114, Jul. 2012.
39. E. Rotem, A. Naveh, D. Rajwan, A. Ananthakrishnan, and E. Weissmann, "Power-management architecture of the intel microarchitecture code-named sandy bridge," IEEE Micro, vol. 32, no. 2, pp. 20-27, March-April 2012.
40. NVIDIA, "NVML API Reference Manual," 2012.
41. S. Hong and H. Kim, "An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness," in Proceedings of the 36th annual International Symposium on Computer Architecture (ISCA). New York, NY, USA: ACM, 2009, pp. 152-163.
42. S. S. Baghsorkhi, M. Delahaye, S. J. Patel, W. D. Gropp, and W. mei W. Hwu, "An adaptive performance modeling tool for GPU architectures," SIGPLAN Not., vol. 45, no. 5, pp. 105-114, Jan. 2010.
43. Y. Zhang and J. D. Owens, "A quantitative performance analysis model for gpu architectures," in Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture, ser. HPCA '11. Washington, DC, USA: IEEE Computer Society, 2011, pp. 382-393.
44. C. Lively, X. Wu, V. Taylor, S. Moore, H.-C. Chang, C.-Y. Su, and K. Cameron, "Power-aware predictive models of hybrid (MPI/OpenMP) scientific applications on multicore systems," Computer Science - Research and Development, pp. 1-9, 2011, 10.1007/s00450-011-0190-0.
45. B. Subramaniam and W.-C. Feng, "Statistical power and performance modeling for optimizing the energy efficiency of scientific computing," in Proceedings of the 2010 IEEE/ACM Int'l Conference on Green Computing and Communications & Int'l Conference on Cyber, Physical and Social Computing, ser. GREENCOM-CPSCOM '10. Washington, DC, USA: IEEE Computer Society, 2010, pp. 139-146.
46. S. Hong and H. Kim, "An integrated GPU power and performance model," SIGARCH Comput. Archit. News, vol. 38, no. 3, pp. 280-289, Jun. 2010.
47. C. Su, D. Li, D. Nikolopoulos, K. Cameron, B. de Supinski, and E. Leon, "Model-based, memory-centric performance and power optimization on numa multiprocessors," in IEEE International Symposium on Workload Characterization, Nov. 2012.
48. R. Gonzalez and M. Horowitz, "Energy dissipation in general purpose microprocessors," IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1277-1284, sep 1996.
49. C. Bekas and A. Curioni, "A new energy-aware performance metric," in Proceedings of the International Conference on Energy-Aware High-Performance Computing (EnA-HPC), Hamburg, Germany, Sep. 2010.
50. S. Sharma, C.-H. Hsu, and W.-C. Feng, "Making a case for a Green500 list," in 20th IEEE International Parallel and Distributed Processing Symposium (IPDPS), April 2006.
51. B. Subramaniam andW.-C. Feng, "The Green Index: A metric for evaluating system-wide energy efficiency in HPC systems," in 8th IEEE Workshop on High-Performance, Power-Aware Computing (HPPAC), Shanghai, China, May 2012.
52. J. W. Choi and R. Vuduc, "A roofline model of energy," Georgia Institute of Technology, School of Computational Science and Engineering, Atlanta, GA, USA, Tech. Rep. GT-CSE-12-01, December 2012.