Characterization and parameterization of a pipeline reconfigurable FPGA

Proceedings - IEEE Symposium on FPGAs for Custom Computing Machines, FCCM 1998

Volumn 1998-April, Issue , 1998, Pages 1-2

  Moe, M ^a   Schmit, H ^a   Goldstein, S C ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURE; COMPUTATION THEORY; COMPUTERS; ECONOMIC AND SOCIAL EFFECTS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); PIPELINES; RECONFIGURABLE ARCHITECTURES;

DESIGN TRADEOFF; GENERIC MODELING; LOGIC BLOCKS; LUT SIZE; PARAMETERIZING; RECONFIGURABLE; RECONFIGURABLE FPGA;

RECONFIGURABLE HARDWARE;

EID: 84884790518     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPGA.1998.707923     Document Type: Conference Paper

References (5)

1. S. Cadambi, J. Weener, H. Schmit, S. C. Goldstein, and D. E. Thomas, "Managing Pipeline Reconfigurable FPGAs," In Sixth International ACM/SIGDA Symposium on Field- Programmable Gate Arrays. ACM, February 1997.
2. D. Cherepacha and D. Lewis. "A Datapath Oriented Architecture for FPGAs." In Second International ACM/SIGDA Workshop on Field-Programmable Gate Arrays. ACM, February 1994.
3. A. DeHon, Reconfigurable Architectures for General-Purpose Computing. Ph.D. Thesis, AI Technical Report 1586, MIT Artificial Intelligence Laboratory, September 1996.
4. S. Singh, J. Rose, P. Chow, D. Lewis, "The Effect of Logic Block Architecture on FPGA Performance," IEEE JSSC, Vol. 27 No. 3, pp. 281-287, March 1992.
5. Schmit, H. "Incremental Reconfiguration for Pipelined Applications," Proceedings of IEEE Symposium on FPGAs for Custom Computing Machines, pp. 47-55, 1997.