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Volumn , Issue , 2000, Pages 667-672

Multi-way partitioning using bi-partition heuristics

Author keywords

[No Author keywords available]

Indexed keywords

CAD TOOL; HIERARCHICAL APPROACH; MULTI-PASS; PARTITION PROBLEM; UPPER BOUND;

EID: 84884681382     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368434.368865     Document Type: Conference Paper
Times cited : (12)

References (20)
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    • IEEE
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    • Cong, J.1    Li, H.P.2    Lim, S.K.3    Shibuya, T.4    Xu, D.5
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    • VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement Techniques
    • IEEE
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    • Karypis, G.1    Aggarwal, R.2    Kumar, V.3    Shekhar, S.4
  • 13
    • 0032681035 scopus 로고    scopus 로고
    • Multilevel k-way Hypergraph Partitioning
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.