-
2
-
-
0033706197
-
A survey of design techniques for system-level dynamic power management
-
Jun
-
L. Benini, A. Bogliolo, and G. De Micheli, "A survey of design techniques for system-level dynamic power management," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8, no. 3, pp. 299-316, Jun. 2000.
-
(2000)
IEEE Trans. Very Large Scale Integr. (VLSI) Syst
, vol.8
, Issue.3
, pp. 299-316
-
-
Benini, L.1
Bogliolo, A.2
De Micheli, G.3
-
3
-
-
84944403811
-
Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction
-
R. Kumar, K. I. Farkas, N. P. Jouppi, P. Ranganathan, and D. M. Tullsen, "Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction," in Proc. Int. Symp. Microarch., 2003, pp. 81-92.
-
(2003)
Proc. Int. Symp. Microarch
, pp. 81-92
-
-
Kumar, R.1
Farkas, K.I.2
Jouppi, N.P.3
Ranganathan, P.4
Tullsen, D.M.5
-
4
-
-
52649086943
-
Learning and leveraging the relationship between architecture-level measurements and individual user satisfaction
-
A. Shye, B. Ozisikyilmaz, A. Mallik, G. Memik, P. Dinda, R. Dick, and A. Choudhary, "Learning and leveraging the relationship between architecture-level measurements and individual user satisfaction," in Proc. Int. Symp. Comput. Arch., 2008, pp. 427-438.
-
(2008)
Proc. Int. Symp. Comput. Arch
, pp. 427-438
-
-
Shye, A.1
Ozisikyilmaz, B.2
Mallik, A.3
Memik, G.4
Dinda, P.5
Dick, R.6
Choudhary, A.7
-
7
-
-
77952256041
-
Conservation cores: Reducing the energy of mature computations
-
Mar
-
G. Venkatesh, J. Sampson, N. Goulding, S. Garcia, V. Bryksin, J. Lugo-Martinez, S. Swanson, and M. B. Taylor, "Conservation cores: Reducing the energy of mature computations," in Proc. Int. Conf. Arch. Support Program. Lang. Operat. Syst., Mar. 2010, pp. 205-218.
-
(2010)
Proc. Int. Conf. Arch. Support Program. Lang. Operat. Syst.
, pp. 205-218
-
-
Venkatesh, G.1
Sampson, J.2
Goulding, N.3
Garcia, S.4
Bryksin, V.5
Lugo-Martinez, J.6
Swanson, S.7
Taylor, M.B.8
-
8
-
-
79955424857
-
The GreenDroid mobile application processor: An architecture for silicon's dark future
-
Mar.-Apr.
-
N. Goulding-Hotta, J. Sampson, G. Venkatesh, S. Garcia, J. Auricchio, P. Huang, M. Arora, S. Nath, V. Bhatt, J. Babb, S. Swanson, and M. Taylor, "The GreenDroid mobile application processor: An architecture for silicon's dark future," IEEE Micro, vol. 31, no. 2, pp. 86-95, Mar.-Apr. 2011.
-
(2011)
IEEE Micro
, vol.31
, Issue.2
, pp. 86-95
-
-
Goulding-Hotta, N.1
Sampson, J.2
Venkatesh, G.3
Garcia, S.4
Auricchio, J.5
Huang, P.6
Arora, M.7
Nath, S.8
Bhatt, V.9
Babb, J.10
Swanson, S.11
Taylor, M.12
-
9
-
-
77957951795
-
Analysis of dynamic voltage scaling for system level energy management
-
G. Dhiman, K. Pusukuri, and T. Rosing, "Analysis of dynamic voltage scaling for system level energy management," in Proc. USENIX Workshop Power Aware Comput. Syst., 2008, p. 9.
-
(2008)
Proc. USENIX Workshop Power Aware Comput. Syst
, pp. 9
-
-
Dhiman, G.1
Pusukuri, K.2
Rosing, T.3
-
10
-
-
77954986440
-
Energyperformance tradeoffs in processor architecture and circuit design: A marginal cost analysis
-
O. Azizi, A. Mahesri, B. Lee, S. Patel, and M. Horowitz, "Energyperformance tradeoffs in processor architecture and circuit design: A marginal cost analysis," in Proc. Int. Symp. Comput. Arch., 2010, pp. 26-36.
-
(2010)
Proc. Int. Symp. Comput. Arch
, pp. 26-36
-
-
Azizi, O.1
Mahesri, A.2
Lee, B.3
Patel, S.4
Horowitz, M.5
-
11
-
-
33847724635
-
A 256-kb 65-nm sub-threshold SRAM design for ultra-low-voltage operation
-
DOI 10.1109/JSSC.2006.891726
-
B. H. Calhoun and A. P. Chandrakasan, "A 256-kb 65-nm sub-threshold SRAM design for ultralow-voltage operation," IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 680-688, Mar. 2007. (Pubitemid 46376044)
-
(2007)
IEEE Journal of Solid-State Circuits
, vol.42
, Issue.3
, pp. 680-688
-
-
Calhoun, B.H.1
Chandrakasan, A.P.2
-
12
-
-
84874536912
-
Advanced channel engineering achieving aggressive reduction of VT variation for ultralow-power applications
-
Mar
-
K. Fujita, Y. Torii, M. Hori, J. Oh, L. Shifren, P. Ranade, M. Nakagawa, K. Okabe, T. Miyake, K. Ohkoshi, M. Kuramae, T. Mori, T. Tsuruta, S. Thompson, and T. Ema, "Advanced channel engineering achieving aggressive reduction of VT variation for ultralow-power applications," in Proc. IEEE Int. Electron. Devices Meeting, Mar. 2011, pp. 32.3.1-32.3.4.
-
(2011)
Proc. IEEE Int. Electron. Devices Meeting
, pp. 3231-3234
-
-
Fujita, K.1
Torii, Y.2
Hori, M.3
Oh, J.4
Shifren, L.5
Ranade, P.6
Nakagawa, M.7
Okabe, K.8
Miyake, T.9
Ohkoshi, K.10
Kuramae, M.11
Mori, T.12
Tsuruta, T.13
Thompson, S.14
Ema, T.15
-
13
-
-
80155199503
-
-
Intel Corporation Santa Clara, CA
-
Intel Corporation. (2008). Intel Atom Processor Z5xx Series, Santa Clara, CA [Online]. Available: http://versalogic.com/support/Downloads/PDF/Intel-Atom- Datasheet.pdf
-
(2008)
Intel Atom Processor Z5xx Series
-
-
-
14
-
-
0037897397
-
A minimal algorithm for the multiple-choice knapsack problem
-
Jun
-
D. Pisinger, "A minimal algorithm for the multiple-choice knapsack problem," Eur. J. Operat. Res., vol. 83, no. 2, pp. 394-410, Jun. 1995.
-
(1995)
Eur. J. Operat. Res
, vol.83
, Issue.2
, pp. 394-410
-
-
Pisinger, D.1
-
15
-
-
84884587586
-
-
Sun OpenSPARC Project
-
Sun OpenSPARC Project [Online]. Available: http://www.sun.com/processors/ opensparc/
-
-
-
-
16
-
-
84884588812
-
FabScalar
-
N. Choudhary, S. Wadhavkar, T. Shah, S. Navada, H. Najaf-Abadi, and E. Rotenberg, "FabScalar," in Proc. Workshop Arch. Res. Prototyp., 2009, pp. 1-12.
-
(2009)
Proc. Workshop Arch. Res. Prototyp
, pp. 1-12
-
-
Choudhary, N.1
Wadhavkar, S.2
Shah, T.3
Navada, S.4
Najaf-Abadi, H.5
Rotenberg, E.6
-
22
-
-
79951560872
-
Challenges and directions for low-voltage SRAM
-
Jan.-Feb.
-
M. Qazi, M. Sinangil, and A. Chandrakasan, "Challenges and directions for low-voltage SRAM," IEEE Trans. Des. Test Comput., vol. 28, no. 1, pp. 32-43, Jan.-Feb. 2011.
-
(2011)
IEEE Trans. Des. Test Comput
, vol.28
, Issue.1
, pp. 32-43
-
-
Qazi, M.1
Sinangil, M.2
Chandrakasan, A.3
-
23
-
-
33846564061
-
Standard cell characterization considering lithography induced variations
-
DOI 10.1145/1146909.1147111, 2006 43rd ACM/IEEE Design Automation Conference, DAC'06
-
K. Cao, S. Dobre, and J. Hu, "Standard cell characterization considering lithography induced variations," in Proc. Design Autom. Conf., 2006, pp. 801-804. (Pubitemid 47114003)
-
(2006)
Proceedings - Design Automation Conference
, pp. 801-804
-
-
Cao, K.1
Dobre, S.2
Hu, J.3
-
24
-
-
0030676681
-
Complexity-effective superscalar processors
-
S. Palacharla, N. Jouppi, and J. Smith, "Complexity-effective superscalar processors," in Proc. Int. Symp. Comput. Arch., 1997, pp. 206-218.
-
(1997)
Proc. Int. Symp. Comput. Arch
, pp. 206-218
-
-
Palacharla, S.1
Jouppi, N.2
Smith, J.3
|