Low-power ferroelectric random access memory embedded in 180nm analog friendly CMOS technology

2013 5th IEEE International Memory Workshop, IMW 2013

Volumn , Issue , 2013, Pages 128-131

  Udayakumar, K R ^a   San, T ^a   Rodriguez, J ^a   Chevacharoenkul, S ^a   Frystak, D ^a   Rodriguez Latorre, J ^a   Zhou, C ^a   Ball, M ^a   Ndai, P ^a   Madan, S ^a   McAdams, H ^a   Summerfelt, S ^a   Moise, T ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

180nm analog CMOS; Ferroelectric; non volatile memory; process integration; PZT; reliability

Indexed keywords

ANALOG CMOS; ANALOG COMPONENTS; ELECTRICAL CHARACTERISTIC; FERROELECTRIC RANDOM ACCESS MEMORY; NON-VOLATILE MEMORY; PB FREE SOLDERS; PROCESS INTEGRATION; PZT;

CMOS INTEGRATED CIRCUITS; CONSUMER ELECTRONICS; DATA STORAGE EQUIPMENT; FERROELECTRIC MATERIALS; LEAD; RELIABILITY;

FERROELECTRIC DEVICES;

EID: 84883670495     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IMW.2013.6582115     Document Type: Conference Paper

References (6)

1. T. Moise, et al., "Demonstration of a 4Mb, high density ferroelectric memory embedded within a 130nm, 5LM Cu/FSG logic process, " IEEE IEDM Digest, pp. 535-538, Dec. 2002.
2. K. R. Udayakumar, et al., "Bit distribution and reliability of high density 1. 5V ferroelectric random access memory embedded with 130nm, 5lm copper CMOS logic, " Jpn. Jl. Appl. Phys., vol. 45, no. 4B, pp. 3202-3206, 2006.
3. S. Aggarwal, K. R. Udayakumar, and J. A. Rodriguez, "Stoichiometry and phase purity of Pb(Zr, Ti)O3 thin films deposited by MOCVD, " Jl. Appl. Phys., vol. 100, 064103, 2006.
4. J. Rodriguez, et al., "Reliability of FRAM embedded within 130nm CMOS, " IEEE IRPS Proceedings, pp. 600-608, 2010.
5. IPC/JEDEC J-STD-020D. 1(Joint Industry Standard), Mar. 2008.
6. N. Setter, et al., "Ferroelectric thin films: review of materials, properties and applications, " Jl. Appl. Phys., vol. 100, 051606, 2008.