A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2013, Pages

  Noguchi, Hiroki ^a   Kushida, Keiichi ^a   Ikegami, Kazutaka ^a   Abe, Keiko ^a   Kitagawa, Eiji ^a   Kashiwada, Saori ^a   Kamata, Chikayoshi ^a   Kawasumi, Atsushi ^a   Hara, Hiroyuki ^a   Fujita, Shinobu ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE POWER; AREA REDUCTION; DUAL CELLS; HIGH SPEED; NON-VOLATILE; PERPENDICULAR MTJ; SENSING SCHEMES; STT-MRAM;

CACHE MEMORY; MAGNETIC DEVICES; STATIC RANDOM ACCESS STORAGE;

MRAM DEVICES;

EID: 84883440896     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. K. Abe et al., IEDM Tech. Dig., pp.243-246, 2012.
2. E. Kitagawa et al., IEDM Tech. Dig., pp.677-680, 2012.
3. R. Nebashi et al., ISSCC Dig. Tech Papers, pp.462-463, 2009.
4. K. Tsuchida et al., ISSCC Dig. Tech. Papers, pp.258-260, 2010.
5. J. P. Kim et al., Symposium on VLSI Circuits, pp.296-297, 2011.
6. T. Ohsawa et al., Symposium on VLSI Tech., pp.46-47, 2012.
7. The gem5 simulator: http://gem5.org/.
8. SPEC CPU2006 benchmark suite: http://www.spec.org/.
9. CACTI LOP SRAM: http://www.hpl.hp.com/research/cacti/.