Hardware acceleration of the robust header compression (RoHC) algorithm

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2013, Pages 293-296

  Al Obaidi, Mohammed ^a   Kittur, Harshavardhan ^a   Andersson, Hakan ^b   Owall, Viktor ^a  

^a LUND UNIVERSITY   (Sweden)

^b ERICSSON RESEARCH   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL LEVELS; COMPRESSION ALGORITHMS; CYCLIC REDUNDANCY CHECK; HARDWARE ACCELERATION; HARDWARE RESOURCES; LEAST SIGNIFICANT BITS; ROBUST HEADER COMPRESSION; SYSTEM THROUGHPUT;

ALGORITHMS; INTERNET TELEPHONY; TABLE LOOKUP; THROUGHPUT; WIRELESS TELECOMMUNICATION SYSTEMS;

HARDWARE;

EID: 84883331261     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2013.6571840     Document Type: Conference Paper

References (6)

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2. D. Szczesny, A. Showk, S. Hessel, A. Bilgic, U. Hildebrand, and V. Frascolla, "Performance analysis of lte protocol processing on an arm based mobile platform," in International Symposium on System-on-Chip, 2009. SOC 2009. IEEE, 2009, pp. 056-063.
3. D. Taylor, A. Herkersdorf, A. Doering, and G. Dittmann, "Robust header compression (rohc) in next-generation network processors," IEEE/ACM Transactions on Networking (TON), vol. 13, no. 4, pp. 755-768, 2005.
4. E. Stavinov, "A practical parallel crc generation method," Circuit Cellar- The Magazine For Computer Applications, vol. 31, no. 234, 2010.
5. M. Al-Obaidi and H. Kittur, "Hardware acceleration of robust header compression (rohc)," Master's thesis, Lund University, 2012.
6. S. T. French space agency (CNES), Thales Alenia and V. Technologies, "Rohc-1.3.1 library," acessed 19-August-2012. [Online]. Available: {http://launchpad.net/rohc/}