Transparent trace-based binary acceleration for reconfigurable HW/SW systems

IEEE Transactions on Industrial Informatics

Volumn 9, Issue 3, 2013, Pages 1625-1634

  Bispo, Joao ^a,b   Paulino, Nuno ^b,c   Cardoso, ^b,c   Ferreira, ^b,c  

^a INESC ID   (Portugal)

^b UNIVERSITY OF PORTO   (Portugal)

^c UNIVERSITY OF PORTO   (Portugal)

Author keywords

Binary translation; hardware accelerator; instruction traces; megablock; reconfigurable computing

Indexed keywords

BINARY TRANSLATION; HARDWARE ACCELERATORS; INSTRUCTION TRACES; MEGA BLOCKS; RECONFIGURABLE COMPUTING;

RANDOM ACCESS STORAGE; RECONFIGURABLE ARCHITECTURES; RECONFIGURABLE HARDWARE;

MICROPROCESSOR CHIPS;

EID: 84882945924     PISSN: 15513203     EISSN: None     Source Type: Journal    
DOI: 10.1109/TII.2012.2235844     Document Type: Article

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