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Volumn 1300 LNCS, Issue , 1997, Pages 1102-1111

A limitation study into access decoupling

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SCIENCE; COMPUTERS;

EID: 84882709429     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/bfb0002859     Document Type: Conference Paper
Times cited : (3)

References (17)
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  • 3
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    • Tzi cker Chiueh. Sunder: A Programmable Hardware Prefetch Architecture for Numerical Loops. In Proc. Supercomputing '94, pages 488-497, Los Alamitos, CA, USA, Nov 1994. IEEE Comput. Soc, ACM, SIAM, IEEE Comput. Soc. Press.
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    • Chiueh, T.1
  • 6
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    • The perfect club benchmarks, effective performance evaluation of supercomputers
    • Urbana, Illinois May
    • M. Berry et al. The Perfect Club Benchmarks, Effective Performance Evaluation of Supercomputers. Techreport 827, CSRD, LIniversity of Illinois, Urbana-Chmpaign, Urbana, Illinois., May 1989.
    • (1989) Techreport 827, CSRD, LIniversity of Illinois, Urbana-Chmpaign
    • Berry, M.1
  • 7
    • 84882667099 scopus 로고    scopus 로고
    • Evaluating the limits of access decoupling using the latency hiding model
    • G. Jones. Evaluating the Limits of Access Decoupling using the Latency Hiding Model. Technical report, Edinburgh University, 1997.
    • (1997) Technical Report, Edinburgh University
    • Jones, G.1
  • 8
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    • Measuring parallelism in computation intensive scientific/Engineering applications
    • Sept.
    • M. Kumar. Measuring Parallelism in Computation Intensive Scientific/Engineering Applications. IEEE Transactions on Computers, 37(9):1088-1098, Sept. 1988.
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    • Kumar, M.1
  • 9
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    • Oct.
    • L. Kurian, P.T. Hulina, and L.D. Coraor. Memory Latency Effects in Decoupled Architectures. IEEE Trans, on Computers, 43(10):1129-39, Oct. 1994.
    • (1994) IEEE Trans, on Computers , vol.43 , Issue.10 , pp. 1129-1139
    • Kurian, L.1    Hulina, P.T.2    Coraor, L.D.3
  • 10
    • 0025792258 scopus 로고
    • Implementation of the PIPE processor
    • Jan
    • M.K. Farrens and A.R. Pleszkun. Implementation of the PIPE Processor. IEEE Computer, pages 65-70, Jan 1991.
    • (1991) IEEE Computer , pp. 65-70
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  • 11
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    • Decoupled access/Execute computer architectures
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    • J.E. Smith. Decoupled Access/Execute Computer Architectures. ACM Trans, on Computer Systems, 2(4):289-308, Nov. 1984.
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  • 17
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.