A circuit-architecture co-optimization framework for evaluating emerging memory hierarchies

ISPASS 2013 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2013, Pages 140-141

  Dong, Xiangyu ^a   Jouppi, Norman P ^b   Xie, Yuan ^c,d  

^a Qualcomm Technology Inc ^*  (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

^c PENNSYLVANIA STATE UNIVERSITY   (United States)

^d AMD Research   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; ELECTRIC NETWORK ANALYSIS; ENERGY EFFICIENCY; INTEGRATED CIRCUIT MANUFACTURE; RRAM; TIMING CIRCUITS;

CIRCUIT ARCHITECTURES; CO-OPTIMIZATION; EMERGING MEMORY; EMERGING NON-VOLATILE MEMORY TECHNOLOGY; ENERGY EFFICIENT; MEMORY HIERARCHY; MEMORY TECHNOLOGY; PERFORMANCE MODEL;

MEMORY ARCHITECTURE;

EID: 84881463331     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2013.6557163     Document Type: Conference Paper

References (3)

1. X. Dong et al., "PCRAMsim: System-level performance, energy, and area modeling for phase-change RAM," in ICCAD, 2009.
2. E. Ipek et al., "Efficient architectural design space exploration via predictive modeling," ACM TACO, vol. 4, no. 4.
3. S. Li et al., "McPAT: An integrated power, area, and timing modeling framework for multicore and manycore architectures," in MICRO, 2009.