Resilient die-stacked DRAM caches

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2013, Pages 416-427

  Sim, Jaewoong ^a   Loh, Gabriel H ^b   Sridharan, Vilas ^c   O'Connor, Mike ^b  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b AMD Research   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

Cache; Die stacking; Error protection; Reliability

Indexed keywords

CACHE; CACHE ORGANIZATION; CHANNEL FAILURES; DIE STACKING; ERROR CORRECTING CODE; ERROR PROTECTION; HIGH-PERFORMANCE COMPUTING; PERFORMANCE DEGRADATION;

CACHE MEMORY; COMPUTER ARCHITECTURE; RELIABILITY;

FAULT TOLERANCE;

EID: 84881184029     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2485922.2485958     Document Type: Conference Paper

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