Flicker: A dynamically adaptive architecture for power limited multicore systems

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2013, Pages 13-23

  Petrica, Paula ^a,c   Izraelevitz, Adam M ^a   Albonesi, David H ^a   Shoemaker, Christine A ^b  

^a Cornell University ^*  (United States)

^b Cornell University   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ARCHITECTURE; MICRO ARCHITECTURES; MULTICORE ARCHITECTURES; ONLINE OPTIMIZATION; OPTIMIZATION ALGORITHMS; PERFORMANCE IMPROVEMENTS; RESPONSE SURFACE MODELS; RUNNING APPLICATIONS;

ALGORITHMS; SOFTWARE ARCHITECTURE;

PIPELINES;

EID: 84881155497     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2485922.2485924     Document Type: Conference Paper

References (49)

1. D. H. Albonesi et al. Dynamically Tuning Processor Resources with Adaptive Processing. IEEE Computer, December 2003.
2. R. I. Bahar and S. Manne. Power and Energy Reduction Via Pipeline Balancing. In Proceedings of the International Symposium on Computer Architecture, July 2001.
3. R. Balasubramonian, D. H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures. In Proceedings of the International Symposium on Microarchitecture, December 2000.
4. R. Bergamaschi et al. Exploring Power Management in Multi-Core Systems. In Proceedings of the Asia and South Pacific Design Automation Conference, January 2008.
5. R. Bitirgen, E. Ipek, and J. F. Martinez. Coordinated Management of Multiple Interacting Resources in Chip Multiprocessors: A Machine Learning Approach. In Proceedings of the International Symposium on Microarchitecture, November 2008.
6. F. A. Bower, P. G. Shealy, S. Ozev, and D. J. Sorin. Tolerating Hard Faults in Microprocessor Array Structures. In Proceedings of the International Conference on Dependable Systems and Networks, June 2004.
7. G. E. Box and D. W. Behnken. Some New Three Level Designs for the Study of Quantitative Variables. Technometrics, November 1960.
8. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In Proceedings of the International Symposium on Computer Architecture, June 2000.
9. A. Buyuktosunoglu, T. Karkhanis, D. H. Albonesi, and P. Bose. Energy Efficient Co-Adaptive Instruction Fetch and Issue. In Proceedings of the International Symposium on Computer Architecture, June 2003.
10. J. Chen, L. K. John, and D. Kaseridis. Modeling Program Resource Demand using Inherent Program Characteristics. SIGMETRICS Perform. Eval. Rev., June 2011.
11. D.-S. Chiou, D.-C. Juan, Y.-T. Chen, and S.-C. Chang. Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization. In Proceedings of the Design Automation Conference, June 2007.
12. K. Deb. An Efficient Constraint Handling Method for Genetic Algorithms. In Computer Methods in Applied Mechanics and Engineering, June 2000.
13. G. Derringer and D. Suich. Simultaneous Optimization of Several Response Variables. Journal of Quality Technology, October 1980.
14. S. Dropsho et al. Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, September 2002.
15. C. Dubach, T. M. Jones, E. V. Bonilla, and M. F. P. O'Boyle. A Predictive Model for Dynamic Microarchitectural Adaptivity Control. In Proceedings of the International Symposium on Microarchitecture, December 2010.
16. Y. Eckert, S. Manne, M. J. Schulte, and D. A. Wood. Something Old and Something New: P-states Can Borrow Microarchitecture Techniques Too. In Proceedings of the International Symposium on Low Power Electronics and Design, September 2012.
17. H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, and D. Burger. Dark Silicon and the End of Multicore Scaling. In Proceedings of the International Symposium on Computer Architecture, June 2011.
18. D. Folegnani and A. González. Energy-Effective Issue Logic. In Proceedings of the International Symposium on Computer Architecture, July 2001.
19. D. Gibson and D. A. Wood. Forwardflow: A Scalable Core for Power-Constrained CMPs. In Proceedings of the International Symposium on Computer Architecture, June 2010.
20. H.-M. Gutmann. A Radial Basis Function Method for Global Optimization. Journal of Global Optimization, March 2001.
21. J. Harrington. The Desirability Function. In Industrial Quality Control, April 1965.
22. M. C. Huang, J. Renau, and J. Torrellas. Positional Adaptation of Processors: Application to Energy Reduction. In Proceedings of the International Symposium on Computer Architecture, 2003.
23. E. Ipek, O. Mutlu, J. F. Martínez, and R. Caruana. Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. In Proceedings of the International Symposium on Computer Architecture, June 2008.
24. C. Isci, A. Buyuktosunoglu, C.-Y. Cher, P. Bose, and M. Martonosi. An Analysis of Efficient Multi-Core Global Power Management Policies: Maximizing Performance for a Given Power Budget. In Proceedings of the International Symposium on Microarchitecture, December 2006.
25. H. Jiang, M. Marek-Sadowska, and S. R. Nassif. Benefits and Costs of Power-Gating Technique. In Proceedings of the International Conference on Computer Design, October 2005.
26. Khubaib, M. Suleman, M. Hashemi, C. Wilkerson, and Y. N. Patt. MorphCore: An Energy-Efficient Microarchitecture for High Performance ILP and High Throughput TLP. In Proceedings of the International Symposium on Microarchitecture, December 2012.
27. S. Kim, S. Kosonocky, D. Knebel, and K. Stawiasz. Experimental Measurement of A Novel Power Gating Structure with Intermediate Power Saving Mode. In Proceedings of the International Symposium on Low Power Electronics and Design, August 2004.
28. R. Kumar and G. Hinton. A Family of 45nm IA Processors. In International Solid-State Circuits Conference, February 2009.
29. B. C. Lee and D. Brooks. Efficiency Trends and Limits from Comprehensive Microarchitectural Adaptivity. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems, March 2008.
30. B. C. Lee and D. M. Brooks. Accurate and Efficient Regression Modeling for Microarchitectural Performance and Power Prediction. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems, October 2006.
31. B. C. Lee, J. Collins, H. Wang, and D. Brooks. CPR: Composable Performance Regression for Scalable Multiprocessor Models. In Proceedings of the International Symposium on Microarchitecture, November 2008.
32. J. Li and J. Martinez. Dynamic Power-Performance Adaptation of Parallel Computation on Chip Multiprocessors. Proceedings of the International Symposium on High-Performance Computer Architecture, February 2006.
33. J. Mueller, C. Shoemaker, and R. Piche. SO-MI: A Surrogate Model Algorithm for Computationally Expensive Nonlinear Mixed-integer Black-box Global Optimization Problems. Computers and Operations Research, May 2013.
34. P. Petrica, J. A. Winter, and D. H. Albonesi. Dynamic Power Redistribution in Failure Prone CMPs. In Workshop on Energy Efficient Design, June 2010.
35. D. Ponomarev, G. Kucuk, and K. Ghose. Reducing Power Requirements of Instruction Scheduling through Dynamic Allocation of Multiple Datapath Resources. In Proceedings of the International Symposium on Microarchitecture, December 2001.
36. R. G. Regis and C. A. Shoemaker. Local Function Approximation in Evolutionary Algorithms for the Optimization of Costly Functions. IEEE Transactions on Evolutionary Computation, October 2004.
37. R. G. Regis and C. A. Shoemaker. A Stochastic Radial Basis Function Method for the Global Optimization of Expensive Functions. INFORMS Journal on Computing, Fall 2007.
38. R. G. Regis and C. A. Shoemaker. Combining Radial Basis Function Surrogates and Dynamic Coordinate Search in High-dimensional Expensive Black-box Optimization. Engineering Optimization, May 2013.
39. J. Renau, B. Fraguela, J. Tuck, W. Liu, M. Prvulovic, L. Ceze, S. Sarangi, P. Sack, K. Strauss, and P. Montesinos. SESC Simulator. http://sesc.sourceforge.net. 2005.
40. J. Sharkey, A. Buyuktosunoglu, and P. Bose. Evaluating Design Tradeoffs in On-Chip Power Management for CMPs. In Proceedings of the International Symposium on Low Power Electronics and Design, August 2007.
41. K. Shi and D. Howard. Sleep Transistor Design and Implementation - Simple Concepts Yet Challenges To Be Optimum. In International Symposium on VLSI Design, April 2006.
42. D. Tarjan, S. Thoziyoor, and N. Jouppi. Cacti 5.3. HP Laboratories Palo Alto Technical Report, 2005.
43. R. Teodorescu and J. Torrellas. Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors. In Proceedings of the International Symposium on Computer Architecture, June 2008.
44. G. Venkatesh et al. Conservation Cores: Reducing the Energy of Mature Computations. In Proceedings of the International Conference on Architectural Support for Programming Languages and Operating Systems, March 2010.
45. Y. Watanabe, J. D. Davis, and D. A. Wood. WiDGET: Wisconsin Decoupled Grid Execution Tiles. In Proceedings of the International Symposium on Computer Architecture, June 2010.
46. T. F. Wenisch, R. E. Wunderlich, M. Ferdman, A. Ailamaki, B. Falsafi, and J. C. Hoe. SimFlex: Statistical Sampling of Computer System Simulation. IEEE Micro July/August 2006.
47. C. F. J. Wu and M. S. Hamada. Experiments: Planning, Analysis, and Optimization. John Wiley and Sons, Inc., 2009.
48. J. Yi, D. Lilja, and D. Hawkins. A Statistically Rigorous Approach for Improving Simulation Methodology. In Proceedings of the International Symposium of High-Performance Computer Architecture, February 2003.
49. Y. Zhang, D. Parikh, K. Sankaranarayanan, K. Skadron, and M. Stan. HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects. In University of Virginia Technical Report CS-2003-05, 2003.