A 2.4 GHz CMOS Doherty power amplifier with dynamic biasing scheme

Proceedings - 2012 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2012, Pages 93-96

  Onizuka, Kohei ^a   Ikeuchi, Katsuyuki ^a   Saigusa, Shigehito ^a   Otaka, Shoji ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DOHERTY POWER AMPLIFIER; DYNAMIC BIASING; EFFICIENCY IMPROVEMENT; FULLY INTEGRATED; OUTPUT POWER LEVELS; PEAK OUTPUT POWER; SPECTRUM MASK; SUPPLY VOLTAGES;

DOHERTY AMPLIFIERS; STANDARDS;

MOS DEVICES;

EID: 84881057639     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPEC.2012.6522635     Document Type: Conference Paper

References (4)

1. M.Elmala, J.Paramesh, K.Soumyanath, "A 90-nm CMOS Doherty Power Amplifier With Minimum AM-PM Distortion," JSSC, Vol.41, No.6, 2006.
2. E.Kaymaksut, P.Reynaert, "A 2.4 GHz Fully Integrated Doherty Power Amplifier Using Series Combining Transformer," ESSCIRC, Sep.2010.
3. E.Kaymaksut, P.Reynaert, "CMOS Transformer-Based Uneven Doherty Power Amplifier for WLAN Applications," ESSCIRC, Sep.2011.
4. K.Onizuka, S.Saigusa, and S.Otaka, "A +30.5dBm CMOS Doherty Power Amplifier with Reliability Enhancement Technique," to appear in Symposium on VLSI Circuits, 2012