메뉴 건너뛰기




Volumn 48, Issue 8, 2013, Pages 1910-1920

Fully integrated capacitive DC-DC converter with all-digital ripple mitigation technique

Author keywords

Capacitance modulation; Dynamic voltage scaling (DVS); Fully integrated capacitive converter; Ripple mitigation; Time modulation

Indexed keywords

CAPACITANCE MODULATION; CAPACITIVE CONVERTERS; DYNAMIC VOLTAGE SCALING; RIPPLE MITIGATION; TIME MODULATION;

EID: 84880924189     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2013.2259044     Document Type: Article
Times cited : (42)

References (19)
  • 1
    • 77957851934 scopus 로고    scopus 로고
    • "Battery statistics," [Online]. Available: http:// batteryuniversity.com/learn/article/battery-statistics
    • Battery Statistics
  • 4
    • 41549111045 scopus 로고    scopus 로고
    • A high efficiency DC-DC converter using 2 nHintegrated inductors
    • Aug
    • J. Wibben and R. Harjani, "A high efficiency DC-DC converter using 2 nHintegrated inductors," IEEE J. Solid-State Circuits, vol. 43, no. 8, pp. 844-854, Aug. 2008.
    • (2008) IEEE J. Solid-State Circuits , vol.43 , Issue.8 , pp. 844-854
    • Wibben, J.1    Harjani, R.2
  • 5
    • 79960842478 scopus 로고    scopus 로고
    • Fully integrated on-chip DC-DC converter with a 450 × output range
    • Aug
    • S. Kudva and R. Harjani, "Fully integrated on-chip DC-DC converter with a 450 × output range," IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1940-1951, Aug. 2011.
    • (2011) IEEE J. Solid-State Circuits , vol.46 , Issue.8 , pp. 1940-1951
    • Kudva, S.1    Harjani, R.2
  • 10
    • 80052043171 scopus 로고    scopus 로고
    • Design techniques for fully intregrated switched-capacitor DC-DC converters
    • Sep
    • H.-P. Le, S. R. Sanders, and E. Alon, "Design techniques for fully intregrated switched-capacitor DC-DC converters," IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 2120-2131, Sep. 2011.
    • (2011) IEEE J. Solid-State Circuits , vol.46 , Issue.9 , pp. 2120-2131
    • Le, H.-P.1    Sanders, S.R.2    Alon, E.3
  • 12
    • 78650066336 scopus 로고    scopus 로고
    • A fully-integrated switched-capacitor step-down dc-dc converter with digital capacitance modulation in 45 nm cmos
    • Dec
    • Y. K. Ramadass, A. A. Fayed, and A. P. Chandrakasan, "A fully-integrated switched-capacitor step-down dc-dc converter with digital capacitance modulation in 45 nm cmos," IEEE J. Solid-State Circuits, vol. 45, no. 12, pp. 2557-2565, Dec. 2010.
    • (2010) IEEE J. Solid-State Circuits , vol.45 , Issue.12 , pp. 2557-2565
    • Ramadass, Y.K.1    Fayed, A.A.2    Chandrakasan, A.P.3
  • 13
    • 34249821961 scopus 로고    scopus 로고
    • An SC voltage doubler with pseudo-continuous output regulation using a three-stage switchable opamp
    • DOI 10.1109/JSSC.2007.897133
    • H. Lee and P. K. T. Mok, "An SC voltage doubler with pseudo-continuous output regulation using a three-stage switchable opamp," IEEE J. Solid-State Circuits, vol. 42, no. 6, pp. 1216-1229, Jun. 2007. (Pubitemid 46853233)
    • (2007) IEEE Journal of Solid-State Circuits , vol.42 , Issue.6 , pp. 1216-1229
    • Lee, H.1    Mok, P.K.T.2
  • 14
    • 31344455697 scopus 로고    scopus 로고
    • Ultra-Dynamic Voltage scaling (UDVS) using sub-threshold operation and local voltage dithering
    • DOI 10.1109/JSSC.2005.859886
    • B. Calhoun and A. P. Chandrakasan, "Ultra-dynamic voltage scaling (UDVS) using sub-threshold operation and local voltage dithering," IEEE J. Solid-State Circuits, vol. 41, no. 1, pp. 238-245, Jan. 2006. (Pubitemid 43145981)
    • (2006) IEEE Journal of Solid-State Circuits , vol.41 , Issue.1 , pp. 238-245
    • Calhoun, B.H.1    Chandrakasan, A.P.2
  • 15
    • 77649112185 scopus 로고    scopus 로고
    • An ultra-low-energy multi-standard JPEG co-processor in 65 nm cmos with sub/near threshold supply voltage
    • Mar
    • Y. Pu, J. P. D. Gyvez, H. Corporaal, and Y. Ha, "An ultra-low-energy multi-standard JPEG co-processor in 65 nm cmos with sub/near threshold supply voltage," IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 668-680, Mar. 2010.
    • (2010) IEEE J. Solid-State Circuits , vol.45 , Issue.3 , pp. 668-680
    • Pu, Y.1    Gyvez, J.P.D.2    Corporaal, H.3    Ha, Y.4
  • 16
    • 59349118349 scopus 로고    scopus 로고
    • A 32 kb 10 T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm cmos
    • Feb
    • I. J. Chang, J.-J. Kim, S. P. Park, and K. Roy, "A 32 kb 10 T sub-threshold SRAM array with bit-interleaving and differential read scheme in 90 nm cmos," IEEE J. Solid-State Circuits, vol. 44, no. 2, pp. 650-658, Feb. 2009.
    • (2009) IEEE J. Solid-State Circuits , vol.44 , Issue.2 , pp. 650-658
    • Chang, I.J.1    Kim, J.-J.2    Park, S.P.3    Roy, K.4
  • 19
    • 84880918968 scopus 로고    scopus 로고
    • MOSIS wafer acceptance tests
    • "MOSIS wafer acceptance tests," MOSIS [Online]. Available: https://www.mosis.com/cgi-bin/cgiwrap/umosis/swp/params/ibm-013/v15t-8rf-8% lm-dm-c4u10-params.txt
    • MOSIS


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.