An energy efficient 32-nm 20-MB shared on-die L3 cache for Intel® Xeon® processor E5 family

IEEE Journal of Solid-State Circuits

Volumn 48, Issue 8, 2013, Pages 1954-1962

  Huang, Min ^a   Mehalel, Moty ^a   Arvapalli, Ramesh ^a   He, Songnian ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Circuit design; Clock; Low Vccmin; On die cache; Power reduction; Redundancy design; SRAM

Indexed keywords

CIRCUIT DESIGNS; LOW VCCMIN; ON-DIE CACHE; POWER REDUCTIONS; REDUNDANCY DESIGN;

CLOCKS; ENERGY EFFICIENCY; MICROPROCESSOR CHIPS; REDUNDANCY; STATIC RANDOM ACCESS STORAGE;

DESIGN;

EID: 84880917346     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2013.2258815     Document Type: Article

References (7)

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7. M. Huang et al., "An energy efficient 32 nm20MBL3 cache for Intel® Xeon® processor E5 family," presented at the IEEE CICC, Sep. 2012.