-
1
-
-
0027430030
-
Spatiotemporal firing patterns in the frontal cortex of behaving monkeys
-
Abeles M., Bergman H., Margalit E., Vaadia E. Spatiotemporal firing patterns in the frontal cortex of behaving monkeys. Journal of Neurophysiology 1993, 70(4):1629-1638.
-
(1993)
Journal of Neurophysiology
, vol.70
, Issue.4
, pp. 1629-1638
-
-
Abeles, M.1
Bergman, H.2
Margalit, E.3
Vaadia, E.4
-
3
-
-
0033142659
-
Translation-invariant pattern recognition based on synfire chains
-
Arnoldi H., Englmeier K., Brauer W. Translation-invariant pattern recognition based on synfire chains. Biological Cybernetics 1999, 80(6):433-447.
-
(1999)
Biological Cybernetics
, vol.80
, Issue.6
, pp. 433-447
-
-
Arnoldi, H.1
Englmeier, K.2
Brauer, W.3
-
6
-
-
84875055083
-
A learning-enabled neuron array ic based upon transistor models of biological phenomena
-
Brink S., Ramakrishnan S., Hasler P., Wunderlich R., Basu A., Degnan B. A learning-enabled neuron array ic based upon transistor models of biological phenomena. IEEE Transactions on Biomedical Circuits and Systems 2013, 7(1):71-81.
-
(2013)
IEEE Transactions on Biomedical Circuits and Systems
, vol.7
, Issue.1
, pp. 71-81
-
-
Brink, S.1
Ramakrishnan, S.2
Hasler, P.3
Wunderlich, R.4
Basu, A.5
Degnan, B.6
-
7
-
-
47149112951
-
A neuromorphic Avlsi network chip with configurable plastic synapses
-
IEEE
-
Camilleri P., Giulioni M., Dante V., Badoni D., Indiveri G., Michaelis B., et al. A neuromorphic Avlsi network chip with configurable plastic synapses. 7th international conference on hybrid intelligent systems, 2007 2007, 296-301. IEEE.
-
(2007)
7th international conference on hybrid intelligent systems, 2007
, pp. 296-301
-
-
Camilleri, P.1
Giulioni, M.2
Dante, V.3
Badoni, D.4
Indiveri, G.5
Michaelis, B.6
-
8
-
-
84880835965
-
-
Capocaccia, (2010). Exploring network architectures with the facets hardware and PyNN. (accessed: 5/31/12).
-
Capocaccia, (2010). Exploring network architectures with the facets hardware and PyNN. (accessed: 5/31/12). http://capocaccia.ethz.ch/capo/wiki/2010/facetshw10.
-
-
-
-
9
-
-
84867681939
-
Silicon neurons that compute. In Artificial neural networks and machine learning-ICANN 2012
-
Choudhary, S., Sloan, S., Fok, S., Neckar, A., Trautmann, E., & Gao, P. et al. (2012). Silicon neurons that compute. In Artificial neural networks and machine learning-ICANN 2012 (pp. 121-128).
-
(2012)
, pp. 121-128
-
-
Choudhary, S.1
Sloan, S.2
Fok, S.3
Neckar, A.4
Trautmann, E.5
Gao, P.6
-
10
-
-
84887302917
-
Pynn: a common interface for neuronal network simulators
-
Davison A., Brüderle D., Eppler J., Kremkow J., Muller E., Pecevski D., et al. Pynn: a common interface for neuronal network simulators. Frontiers in Neuroinformatics 2008, 2.
-
(2008)
Frontiers in Neuroinformatics
, vol.2
-
-
Davison, A.1
Brüderle, D.2
Eppler, J.3
Kremkow, J.4
Muller, E.5
Pecevski, D.6
-
15
-
-
0034762808
-
Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons
-
Goldberg D.H., Cauwenberghs G., Andreou A.G. Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons. Neural Networks 2001, 14(6-7):781-794.
-
(2001)
Neural Networks
, vol.14
, Issue.6-7
, pp. 781-794
-
-
Goldberg, D.H.1
Cauwenberghs, G.2
Andreou, A.G.3
-
17
-
-
33244465845
-
A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity
-
Indiveri G., Chicca E., Douglas R. A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity. IEEE Transactions on Neural Networks 2006, 17(1):211-221.
-
(2006)
IEEE Transactions on Neural Networks
, vol.17
, Issue.1
, pp. 211-221
-
-
Indiveri, G.1
Chicca, E.2
Douglas, R.3
-
19
-
-
77956006404
-
Hardware and software infrastructure for a family of floating-gate based FPAAs
-
IEEE
-
Koziol S., Schlottmann C., Basu A., Brink S., Petre C., Degnan B., et al. Hardware and software infrastructure for a family of floating-gate based FPAAs. Proceedings of 2010 IEEE international symposium on circuits and systems 2010, 2794-2797. IEEE.
-
(2010)
Proceedings of 2010 IEEE international symposium on circuits and systems
, pp. 2794-2797
-
-
Koziol, S.1
Schlottmann, C.2
Basu, A.3
Brink, S.4
Petre, C.5
Degnan, B.6
-
20
-
-
84880843239
-
-
Winner-take-all networks of o (n) complexity. Tech. rep., DTIC Document.
-
Lazzaro, J., Ryckebusch, S., Mahowald, M., & Mead, C. (1988). Winner-take-all networks of o (n) complexity. Tech. rep., DTIC Document.
-
(1988)
-
-
Lazzaro, J.1
Ryckebusch, S.2
Mahowald, M.3
Mead, C.4
-
21
-
-
4644262757
-
Temporal coding in a silicon network of integrate-and-fire neurons
-
Liu S.-C., Douglas R. Temporal coding in a silicon network of integrate-and-fire neurons. IEEE Transactions on Neural Networks 2004, 15(5):1305-1314.
-
(2004)
IEEE Transactions on Neural Networks
, vol.15
, Issue.5
, pp. 1305-1314
-
-
Liu, S.-C.1
Douglas, R.2
-
22
-
-
84871724333
-
Scaling energy per operation via an asynchronous pipeline
-
Marr B., Degnan B., Hasler P., Anderson D. Scaling energy per operation via an asynchronous pipeline. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2013, 21(1):147-151.
-
(2013)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.21
, Issue.1
, pp. 147-151
-
-
Marr, B.1
Degnan, B.2
Hasler, P.3
Anderson, D.4
-
23
-
-
0002119701
-
Computational architectures for attention
-
Niebur E., Koch C. Computational architectures for attention. The attentive brain 1998, 163-186.
-
(1998)
The attentive brain
, pp. 163-186
-
-
Niebur, E.1
Koch, C.2
-
28
-
-
40649092872
-
Implementing synaptic plasticity in a VLSI spiking neural network model
-
IEEE
-
Schemmel J., Grubl A., Meier K., Mueller E. Implementing synaptic plasticity in a VLSI spiking neural network model. International joint conference on neural networks, 2006 2006, 1-6. IEEE.
-
(2006)
International joint conference on neural networks, 2006
, pp. 1-6
-
-
Schemmel, J.1
Grubl, A.2
Meier, K.3
Mueller, E.4
-
29
-
-
0002594179
-
Spike arrival times: a highly efficient coding scheme for neural networks
-
Thorpe S. Spike arrival times: a highly efficient coding scheme for neural networks. Parallel processing in neural systems 1990, 91-94.
-
(1990)
Parallel processing in neural systems
, pp. 91-94
-
-
Thorpe, S.1
-
31
-
-
84874143086
-
65k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing
-
IEEE
-
Yu T., Park J., Joshi S., Maier C., Cauwenberghs G. 65k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing. 2012 IEEE biomedical circuits and systems conference 2012, 21-24. IEEE.
-
(2012)
2012 IEEE biomedical circuits and systems conference
, pp. 21-24
-
-
Yu, T.1
Park, J.2
Joshi, S.3
Maier, C.4
Cauwenberghs, G.5
|