Self-aligned gate nanopillar In0.53Ga0.47As vertical tunnel transistor

Device Research Conference - Conference Digest, DRC

Volumn , Issue , 2011, Pages 203-204

  Mohata, D K ^a   Bijesh, R ^a   Saripalli, V ^a   Mayer, T ^a   Datta, S ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DOUBLE-GATE DEVICE; FABRICATION PROCESS; HIGH DRIVE CURRENT; HIGH-PERFORMANCE LOGIC APPLICATIONS; SELF-ALIGNED GATE; TRANSISTOR PERFORMANCE; TUNNEL FIELD EFFECT TRANSISTOR; TUNNEL TRANSISTORS;

GERMANIUM; SILICON;

FIELD EFFECT TRANSISTORS;

EID: 84880710198     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2011.5994498     Document Type: Conference Paper

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