Breaking the on-chip latency barrier using SMART

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2013, Pages 378-389

  Krishna, Tushar ^a   Chen, Chia Hsin Owen ^a   Kwon, Woo Cheol ^a   Peh, Li Shiuan ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE COHERENCE PROTOCOLS; FULL-SYSTEM SIMULATION; MICRO ARCHITECTURES; MULTI-HOP PATH; MULTIPLE HOPS; NETWORK LATENCIES; ON-CHIP NETWORKS; TRAFFIC PATTERN;

COMPUTER ARCHITECTURE; DIGITAL STORAGE; ROUTERS; SUPERCOMPUTERS;

DESIGN;

EID: 84880266578     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2013.6522334     Document Type: Conference Paper

References (36)

1. http://www.tilera.com/products/processors/TILE-Gx-Family.
2. http://projects.csail.mit.edu/angstrom.
3. http://www-flash.stanford.edu/apps/SPLASH/.
4. http://www.windriver.com/products/simics.
5. N. Agarwal, T. Krishna, L.-S. Peh, and N. K. Jha. GARNET: A detailed on-chip network model inside a full-system simulator. In ISPASS, pages 33-42, 2009.
6. A. R. Alameldeen and D. A. Wood. Variability in architectural simulations of multi-threaded workloads. In HPCA, 2003.
7. J. Bainbridge and S. Furber. Chain: A delay-insensitive chip area interconnect. IEEE Micro, 22(5):16-23, Sept 2002.
8. J. Balfour and W. J. Dally. Design tradeoffs for tiled CMP on-chip networks. In ICS, pages 187-198, 2006.
9. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: Characterization and architectural implications. In PACT, 2008.
10. T. Bjerregaard and J. Sparso. A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip. In DATE, pages 1226-1231, 2005.
11. W. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann Pub., 2003.
12. B. Grot, J. Hestness, S.W. Keckler, and O. Mutlu. Kilo-NOC: A heterogeneous network-on-chip architecture for scalability and service guarantees. In ISCA, pages 401-412, 2011.
13. B. Grot et al. Express cube topologies for on-chip interconnects. In HPCA, pages 163-174, 2009.
14. R. Haring et al. The IBM Blue Gene/Q Compute Chip. IEEE Micro, 32(2):48-60, Mar 2012.
15. Y. Hoskote et al. A 5-GHz mesh interconnect for a teraflops processor. IEEE Micro, 27(5):51-61, Sept. 2007.
16. J. Howard et al. A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS. In ISSCC, pages 108-109, 2010.
17. T. N. K. Jain, P. V. Gratz, A. Sprintson, and G. Choi. Asynchronous bypass channels: Improving performance for multisynchronous nocs. pages 51-58, 2010.
18. D. Johnson et al. Rigel: A 1,024-core single-chip accelerator architecture. IEEE Micro, 31(4):30-41, Jul 2011.
19. Y.-H. Kao et al. CNoC: High-radix clos network-on-chip. TCAD, 30(12):1897-1910, 2011.
20. B. Kim and V. Stojanovic. Equalized interconnects for onchip networks: modeling and optimization framework. In ICCAD, pages 552-559, 2007.
21. J. Kim et al. Microarchitecture of a high-radix router. In ISCA, pages 420-431, 2005.
22. J. Kim et al. Flattened butterfly topology for on-chip networks. In MICRO, pages 172-182, 2007.
23. T. Krishna, L.-S. Peh, B. M. Beckmann, and S. K. Reinhardt. Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication. In MICRO, pages 71-82, 2011.
24. T. Krishna et al. Express Virtual Channels with capacitively driven global links. IEEE Micro, 29(4):48-61, 2009.
25. T. Krishna et al. SWIFT: A SWing-reduced Interconnect For a Token-based network-on-chip in 90nm CMOS. In ICCD, pages 439-446, 2010.
26. A. Kumar et al. A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. In ICCD, pages 63-70, 2007.
27. A. Kumar et al. Token Flow Control. In MICRO, 2008.
28. G. Kurian et al. ATAC: A 1000-core cache-coherent processor with on-chip optical network. In PACT, pages 477-488, 2010.
29. M. M. K. Martin et al. Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset. CAN, 2005.
30. H. Matsutani et al. Prediction router: Yet another low latency on-chip router architecture. In MICRO, pages 367-378, 2009.
31. R. Mullins et al. Low-latency virtual-channel routers for on-chip networks. In ISCA, pages 188-197, 2004.
32. S. Park et al. Approaching the theoretical limits of a mesh NoC with a 16-node chip prototype in 45nm SOI. In DAC, pages 398-405, 2012.
33. J. Rabaey and A. Chandrakasan. Digital Integrated Circuits: A Design Perspective. Prentice Hall Pub., 2002.
34. S. Scott et al. The BlackWidow high-radix clos network. In ISCA, pages 16-28, 2006.
35. C. Sun et al. DSENT-A tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling. In NOCS, pages 201-210, 2012.
36. D. Wentzlaff et al. On-chip interconnection architecture of the Tile Processor. IEEE Micro, 27(5):15-31, Sept. 2007.