Accelerating GPGPU architecture simulation

Performance Evaluation Review

Volumn 41, Issue 1 SPEC. ISS., 2013, Pages 331-332

  Yu, Zhibin ^a   Eeckhout, Lieven ^b   Goswami, Nilanjan ^c   Li, Tao ^c   John, Lizy K ^d   Jin, Hai ^e   Xu, Chengzhong ^a,f  

^a SHENZHEN INSTITUTES OF ADVANCED TECHNOLOGY   (China)

^b GHENT UNIVERSITY   (Belgium)

^c UNIVERSITY OF FLORIDA   (United States)

^d The University of Texas at Austin   (United States)

^e HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (China)

^f Wayne State University   (United States)

Author keywords

General purpose graphics processing unit (GPGPU); Micro architecture simulation; Performance

Indexed keywords

COMPUTATIONAL POWER; GENERAL PURPOSE GRAPHICS PROCESSING UNIT (GPGPU); GPGPU ARCHITECTURES; GRAPHICS PROCESSING UNITS; MICRO ARCHITECTURES; PARALLEL APPLICATION; PERFORMANCE; STATIC CHARACTERISTIC;

ARCHITECTURE; COMPUTER GRAPHICS; COMPUTER SYSTEMS; PARALLEL ARCHITECTURES;

PROGRAM PROCESSORS;

EID: 84880232585     PISSN: 01635999     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2494232.2465540     Document Type: Conference Paper

References (4)

1. NVIDIA CORPORATION, CUDA Programming Guide Version 3.0, 2010.
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3. Wunderlich. R. E, Wenisch. T. F, Fasafi. B, and Hoe. J. C. SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. In Proceedings of the 30th Annual International Symposium on Computer Architecture (ISCA), pp. 84-95, June 2003.
4. Sherwood. T, Perelman. E, Hamerly. G, and Calder. B. Automatically Characterizing Large Scale Program Behavior. In Proceedings of the 10th International Conference on Architecture Support for Programming Languages and Operating Systems (ASPLOS), pp. 45-57, Oct 2002.