Engineering nanowire n-MOSFETs at Lg<8 nm

IEEE Transactions on Electron Devices

Volumn 60, Issue 7, 2013, Pages 2171-2177

  Mehrotra, Saumitra R ^a   Kim, Sunggeun ^a   Kubis, Tillmann ^a   Povolotskyi, Michael ^a   Lundstrom, Mark S ^a   Klimeck, Gerhard ^a  

^a Purdue University   (United States)

Author keywords

InAs; nanowire; quantum transport; Si; source drain tunneling; strain; tight binding (TB) approach

Indexed keywords

INAS; METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR; ON STATE CURRENT; PERFORMANCE LIMITING FACTOR; QUANTUM TRANSPORT; QUANTUM TRANSPORT SIMULATIONS; SOURCE-DRAIN; TIGHT-BINDING APPROACHES;

CRYSTAL ORIENTATION; NANOWIRES; QUANTUM ELECTRONICS; SILICON; STRAIN;

MOSFET DEVICES;

EID: 84879971502     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2013.2263806     Document Type: Article

References (28)

1. C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, R. Grover, W. Han, D. Hanken, M. Hattendorf, P. Hentges, R. Heussner, J. Hicks, D. Ingerly, P. Jain, S. Jaloviar, R. James, D. Jones, J. Jopling, S. Joshi, C. Kenyon, H. Liu, R. McFadden, B. McIntyre, J. Neirynck, C. Parker, L. Pipes, I. Post, S. Pradhan, M. Prince, S. Ramey, T. Reynolds, J. Roesler, J. Sandford, J. Seiple, P. Smith, C. Thomas, D. Towner, T. Troeger, C. Weber, P. Yashar, K. Zawadzki, and K. Mistry, "A 22 nm high performance and low-power CMOS technology featuring fully-depleted trigate transistors, self-aligned contacts and high density MIM capacitors," in Proc. Symp. VLSI Technol., Jun. 2012, pp. 131-132.
2. (2012, Apr. 10). International Technology Roadmap for Semiconductors [Online]. Available: http://www.itrs.net/links/2011itrs/home2011.htm
3. M. Luisier, M. Lundstrom, D. Antoniadis, and J. Bokor, "Ultimate device scaling: Intrinsic performance comparisons of carbon-based, InGaAs, and Si field-effect transistors for 5 nm gate length," in Proc. IEDM, Dec. 2011, pp. 11.2.1-11.2.4.
4. J. Wang and M. Lundstrom, "Does source-to-drain tunneling limit the ultimate scaling of MOSFETs?" in Proc. IEDM, 2002, pp. 707-710.
5. J. Appenzeller, J. Knoch, M. Bjork, H. Riel, H. Schmid, and W. Riess, "Toward nanowire electronics," IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 2827-2845, Nov. 2008.
6. J. A. del Alamo, "Nanometre-scale electronics with III-V compound semiconductors," Nature, vol. 479, pp. 317-323, Nov. 2011.
7. M. Fischetti, L. Wangt, B. Yut, C. Sachs, P. Asbeck, Y. Taur, and M. Rodwell, "Simulation of electron transport in high-mobility MOSFETs: Density of states bottleneck and source starvation," in Proc. IEEE IEDM, Dec. 2007, pp. 109-112.
8. S. Sylvia, H.-H. Park, M. Khayer, K. Alam, G. Klimeck, and R. Lake, "Material selection for minimizing direct tunneling in nanowire transistors," IEEE Trans. Electron Devices, vol. 59, no. 8, pp. 2064-2069, Aug. 2012.
9. M. Bescond, N. Cavassilas, and M. Lannoo, "Effective-mass approach for n-type semiconductor nanowire MOSFETs arbitrarily oriented," Nanotechnology, vol. 18, no. 25, p. 255201, 2007.
10. P. Solomon, D. Frank, J. Jopling, C. D'Emic, O. Dokumaci, P. Ronsheim, and W. Haensch, "Tunnel current measurements on P/N junction diodes and implications for future device design," in IEEE IEDM Tech. Dig., Dec. 2003, pp. 9.3.1-9.3.4.
11. T. Yu, R. Wang, R. Huang, J. Chen, J. Zhuge, and Y. Wang, "Investigation of nanowire line-edge roughness in gate-all-around silicon nanowire MOSFETs," IEEE Trans. Electron Devices, vol. 57, no. 11, pp. 2864-2871, Nov. 2010.
12. S. Thompson, G. Sun, Y. S. Choi, and T. Nishida, "Uniaxial- processinduced strained-Si: Extending the CMOS roadmap," IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1010-1020, May 2006.
13. F. Stern and W. Howard, "Properties of semiconductor surface inversion layers in the electric quantum limit," Phys. Rev., vol. 163, no. 3, pp. 816-835, 1967.
14. Y. Liu, N. Neophytou, T. Low, G. Klimeck, and M. Lundstrom, "A tightbinding study of the ballistic injection velocity for ultrathin-body SOI MOSFETs," IEEE Trans. Electron Devices, vol. 55, no. 3, pp. 866-871, Mar. 2008. (Pubitemid 351404546)
15. J.-L. van der Steen, D. Esseni, P. Palestri, L. Selmi, and R. J. E. Hueting, "Validity of the parabolic effective mass approximation in silicon and germanium n-MOSFETs with different crystal orientations," IEEE Trans. Electron Devices, vol. 54, no. 8, pp. 1843-1851, Aug. 2007. (Pubitemid 47260259)
16. N. Kharche, G. Klimeck, D. Kim, J. A. Del Alamo, and M. Luisier, "Multiscale metrology and optimization of ultra-scaled inas quantum well FETs," IEEE Trans. Electron Devices, vol. 58, no. 7, pp. 1963-1971, Jul. 2011.
17. M. Luisier, A. Schenk, W. Fichtner, and G. Klimeck, "Atomistic simulation of nanowires in the sp3d5s? tight-binding formalism: From boundary conditions to strain calculations," Phys. Rev. B, vol. 74, no. 20, pp. 205323-1-205323-12, 2006.
18. T. B. Boykin, G. Klimeck, and F. Oyafuso, "Valence band effectivemass expressions in the sp3d5s? empirical tight-binding model applied to a Si and Ge parametrization," Phys. Rev. B, vol. 69, pp. 115201-1-115201-10, Mar. 2004.
19. T. B. Boykin, G. Klimeck, R. C. Bowen, and F. Oyafuso, "Diagonal parameter shifts due to nearest-neighbor displacements in empirical tight-binding theory," Phys. Rev. B, vol. 66, no. 12, p. 125207, Sep. 2002.
20. T. B. Boykin, M. Luisier, M. Salmani-Jelodar, and G. Klimeck, "Straininduced, off-diagonal, same-atom parameters in empirical tight-binding theory suitable for uniaxial strain applied to a silicon parametrization," Phys. Rev. B, vol. 81, p. 125202, Mar. 2010.
21. M. Luisier and G. Klimeck, "Atomistic full-band simulations of silicon nanowire transistors: Effects of electron-phonon scattering," Phys. Rev. B, vol. 80, no. 15, pp. 155430-1-155430-11, 2009.
22. S. Hasan, M. A. Alam, and M. S. Lundstrom, "Simulation of carbon nanotube FETs including hot-phonon and self-heating effects," IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2352-2361, Sep. 2007. (Pubitemid 351485750)
23. L. Donetti, F. Gámiz, N. Rodriguez, F. Jimenez, and C. Sampedro, "Influence of acoustic phonon confinement on electron mobility in ultrathin silicon on insulator layers," Appl. Phys. Lett., vol. 88, no. 12, pp. 122108-1-122108-3, 2006.
24. Q. Xie, J. Xu, and Y. Taur, "Review and critique of analytic models of MOSFET short-channel effects in subthreshold," IEEE Trans. Electron Devices, vol. 59, no. 6, pp. 1569-1579, Jun. 2012.
25. Y. Morita, S. Migita, W. Mizubayashi, M. Masahara, and H. Ota, "Twostep annealing effects on ultrathin EOT higher-k (k = 40) ALD-HFO2 gate stacks," in Proc. Eur. Solid-State Device Res. Conf., Sep. 2012, pp. 81-84.
26. N. Luisier and G. Klimeck, "Phonon-limited mobility and injection velocity in n-and p-doped ultrascaled nanowire field-effect transistors with different crystal orientations," in Proc. IEEE IEDM, Dec. 2010, pp. 8.6.1-8.6.4.
27. C. Jeong, D. Antoniadis, and M. Lundstrom, "On backscattering and mobility in nanoscale silicon MOSFETs," IEEE Trans. Electron Devices, vol. 56, no. 11, pp. 2762-2769, Nov. 2009.
28. E. Bernard, T. Ernst, B. Guillaumot, N. Vulliet, P. Coronel, T. Skotnicki, S. Deleonibus, and O. Faynot, "Multi-channel field-effect transistor (MCFET)-Part I: Electrical performance and current gain analysis," IEEE Trans. Electron Devices, vol. 56, no. 6, pp. 1243-1251, Jun. 2009.