Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches

Proceedings of the International Conference on Supercomputing

Volumn , Issue , 2013, Pages 491-

  Valero, Alejandro ^a   Sahuquillo, Julio ^a   Petit, Salvador ^a   Duato, José ^a  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

Author keywords

MRU tour; on chip caches; selective refresh

Indexed keywords

DYNAMIC ENERGY; ENERGY AWARE; LAST-LEVEL CACHES; MRU TOURS; ON-CHIP CACHE; PERFORMANCE LOSS; REFRESH MECHANISM; SELECTIVE REFRESH;

SUPERCOMPUTERS;

INFORMATION USE;

EID: 84879831521     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2464996.2467278     Document Type: Conference Paper

References (3)

1. J. Lira et al. Implementing a hybrid SRAM/eDRAM NUCA architecture. In Proc. 18th Int'l Conf. High Perform. Comput., pages 1-10, 2011.
2. A. Valero et al. Combining Recency of Information with Selective Random and a Victim Cache in Last-Level Caches. ACM Trans. Arch. Code Opt., 9(3):16:1-16:20, 2012.
3. C. Wilkerson et al. Reducing Cache Power with Low-Cost, Multi-bit Error-Correcting Codes. In Proc. 37th Int'l Symp. Comput. Arch., pages 83-93, 2010.