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Volumn , Issue , 2013, Pages 491-
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Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches
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Author keywords
MRU tour; on chip caches; selective refresh
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Indexed keywords
DYNAMIC ENERGY;
ENERGY AWARE;
LAST-LEVEL CACHES;
MRU TOURS;
ON-CHIP CACHE;
PERFORMANCE LOSS;
REFRESH MECHANISM;
SELECTIVE REFRESH;
SUPERCOMPUTERS;
INFORMATION USE;
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EID: 84879831521
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/2464996.2467278 Document Type: Conference Paper |
Times cited : (2)
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References (3)
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