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Volumn , Issue , 2013, Pages 491-

Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches

Author keywords

MRU tour; on chip caches; selective refresh

Indexed keywords

DYNAMIC ENERGY; ENERGY AWARE; LAST-LEVEL CACHES; MRU TOURS; ON-CHIP CACHE; PERFORMANCE LOSS; REFRESH MECHANISM; SELECTIVE REFRESH;

EID: 84879831521     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2464996.2467278     Document Type: Conference Paper
Times cited : (2)

References (3)
  • 1
    • 84858044278 scopus 로고    scopus 로고
    • Implementing a hybrid SRAM/eDRAM NUCA architecture
    • J. Lira et al. Implementing a hybrid SRAM/eDRAM NUCA architecture. In Proc. 18th Int'l Conf. High Perform. Comput., pages 1-10, 2011.
    • (2011) Proc. 18th Int'l Conf. High Perform. Comput. , pp. 1-10
    • Lira, J.1
  • 2
    • 84870185944 scopus 로고    scopus 로고
    • Combining Recency of Information with Selective Random and a Victim Cache in Last-Level Caches
    • A. Valero et al. Combining Recency of Information with Selective Random and a Victim Cache in Last-Level Caches. ACM Trans. Arch. Code Opt., 9(3):16:1-16:20, 2012.
    • (2012) ACM Trans. Arch. Code Opt. , vol.9 , Issue.3
    • Valero, A.1
  • 3
    • 77954995377 scopus 로고    scopus 로고
    • Reducing Cache Power with Low-Cost, Multi-bit Error-Correcting Codes
    • C. Wilkerson et al. Reducing Cache Power with Low-Cost, Multi-bit Error-Correcting Codes. In Proc. 37th Int'l Symp. Comput. Arch., pages 83-93, 2010.
    • (2010) Proc. 37th Int'l Symp. Comput. Arch. , pp. 83-93
    • Wilkerson, C.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.