A 50% power reduction scheme for CMOS relaxation oscillator

AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Volumn , Issue , 1999, Pages 154-157

  Song, Byungjoon ^a   Kim, Hwicheol ^a   Choi, Youngdon ^a   Kim, Wonchan ^a  

^a Seoul National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84879378609     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APASIC.1999.824051     Document Type: Conference Paper

References (3)

1. Paul R. Gray and Robert G. Meyer, Analysis and design of Analog Integrated circuits, 2nd ed., New York:Wiley, 1984.
2. Behard Razavi, "A Study of Phase noise in. CMOS Oscilla-tors.," IEEE J. Solid-State Circuits, vol. 31, pp. 331-343, Mar. 1996.
3. Ian A. Young, Jeffrey K. Greason, Keng L. Wong, "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors, " IEEE J. Solid-State Circuits, vol. 27, pp. 1599-1607, Nov. 1992.