CMOS leakage and power reduction in transistors and circuits: Process and layout considerations

Journal of Low Power Electronics and Applications

Volumn 2, Issue 1, 2012, Pages

  Shauly, Eitan N ^a,b  

^a TowerJazz   (Israel)

^b TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

Design aware leakage reduction; Layout optimization; Leakage related stressors; Low leakage; Low power; Transistor scaling

Indexed keywords

EID: 84878790922     PISSN: None     EISSN: 20799268     Source Type: Journal    
DOI: 10.3390/jlpea2010001     Document Type: Review

References (54)

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