An ACL2 model of VHDL for symbolic simulation and formal verification

Proceedings - 13th Symposium on Integrated Circuits and Systems Design

Volumn , Issue , 2000, Pages 269-274

  Moraes Rodrigues, V ^a,b   Borrione, D ^a   Georgelin, P ^a  

^a TIMA LABORATORY   (France)

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Debugging; Engines; Formal verification; Interconnected systems; Logic; Mathematical model; Specification languages; Testing

Indexed keywords

COMPUTER DEBUGGING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; ENGINES; FORMAL LOGIC; INTEGRATED CIRCUITS; LARGE SCALE SYSTEMS; MATHEMATICAL MODELS; MODEL CHECKING; PROGRAM DEBUGGING; SEMANTICS; SPECIFICATION LANGUAGES; SYSTEMS ANALYSIS; TESTING;

COMPONENT PROPERTIES; FIRST ORDER LOGIC; INFINITE NUMBERS; LOGIC; SYMBOLIC SIMULATION; SYSTEM PROPERTY; THEOREM PROVERS; VHDL DESCRIPTION;

FORMAL VERIFICATION;

EID: 84878206547     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBCCI.2000.876041     Document Type: Conference Paper

References (6)

1. D. Borrione, P. Georgelin, and V. Rodrigues. Symbolic simulation and verification of VHDL with ACL2. In International Conference on HDL (HDLCONF'2000), pages 167-182, San Jose, 2000.
2. IEEE Std 1076.6, New York. IEEE Standard for VHDL Register Transfer Level Synthesis, 1999.
3. M. Kaufmann, P. Manolios, and J. S. Moore. Computer-Aided Reasoning: An Approach. Kluwer, 2000.
4. M. Kaufmann and J. S. Moore. An industrial strength theorem prover for a logic based on Common Lisp. IEEE Transactions on Software Engineering, 23(4):203-13, April 1997.
5. K. C. McMillan. Symbolic Model Checking. Kluwer, Boston, 1993.
6. J. S. Moore. Symbolic simulation: An ACL2 approach. In FMCAD'98, pages 334-350, 1998. LNCS 1522.