Effect of SiO2 tunnel layer processes on the characteristics of MONOS charge trap devices with poly-Si channels

Microelectronic Engineering

Volumn 110, Issue , 2013, Pages 6-11

  Na, Heedo ^a   Oh, Jinho ^a   Lee, Kyumin ^a   Kim, Jonggi ^a   Lee, Sunghoon ^b   Lim, Dong Hyeok ^a   Cho, Mann Ho ^a   Sohn, Hyunchul ^a  

^a Yonsei University   (South Korea)

^b Hynix Semiconductor Inc   (South Korea)

Author keywords

Charge trap memory; Flash memory; Poly Si channel; Tunnel layer

Indexed keywords

CHARGE TRAP; F-N TUNNELING; FLAT-BAND VOLTAGE SHIFT; PROGRAM/ERASE; RADICAL OXIDATION; THERMAL OXIDATION; TRAPPED CHARGE; TUNNEL DIELECTRICS;

CHARGE TRAPPING; FLASH MEMORY;

SILICON;

EID: 84877957240     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mee.2013.04.025     Document Type: Article

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