Optimizing Parallel Prefix Operations for the Fermi Architecture

GPU Computing Gems Jade Edition

Volumn , Issue , 2012, Pages 29-38

  Harris, Mark ^a   Garland, Michael ^a  

^a NVIDIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84877899022     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1016/B978-0-12-385963-1.00003-4     Document Type: Chapter

References (12)

1. Blelloch G.E. Vector Models for Data-Parallel Computing 1990, MIT Press, Cambridge, MA.
2. Harris M., Sengupta S., Owens J.D. Parallel prefix sum (scan) with CUDA. GPU Gems 3 (Chapter 39) 2007, 851-876. Addison Wesley, New York. H. Nguyen (Ed.).
3. Sengupta S., Harris M., Zhang Y., Owens J.D. Scan primitives for GPU computing. Graphics Hardware 2007 2007, 97-106.
4. Dotsenko Y., Govindaraju N.K., Sloan P.-P., Boyd C., Manferdelli J. Fast scan algorithms on graphics processors. Proceedings of the 22nd Annual International Conference on Supercomputing 2008, 205-213. http://portal.acm.org/citation.cfm?id=1375527&picked=prox.
5. S. Sengupta, M. Harris, M. Garland, Efficient Parallel scan algorithms for GPUs, Technical Report NVR-2008-003, NVIDIA Corporation, 2008.
6. Billeter M., Olsson O., Assarsson U. Efficient stream compaction on wide SIMD many-core architectures. HPG '09: Proceedings of the Conference on High Performance Graphics 2009 2009, 159-166.
7. D. Merrill, A. Grimshaw, Parallel Scan for Stream Architectures, Technical Report CS2009-14, Department of Computer Science, University of Virginia, 2009.
8. Sengupta S., Harris M., Garland M., Owens J.D. Efficient parallel scan algorithms for many-core GPUs. Scientific Computing with Multicore and Accelerators, Chapman & Hall/CRC Computational Science (Chapter 19) 2011, 413-442. Taylor & Francis, Boca Raton, FL. J. Dongarra, D.A. Bader, J. Kurzak (Eds.).
9. Satish N., Harris M., Garland M. Designing efficient sorting algorithms for manycore GPUs. Proceedings of the 23rd IEEE International Parallel and Distributed Processing Symposium 2009, 1-10.
10. D. Merrill, A. Grimshaw, Revisiting Sorting for GPGPU Stream Architectures, Technical Report CS2010-03, Department of Computer Science, University of Virginia, 2010.
11. NVIDIA Corporation, NVIDIA CUDA Programming Guide, version 4.0. , 2010 (accessed 27.07.11). http://developer.download.nvidia.com/compute/cuda/4_0/toolkit/docs/CUDA_ C_Programming_Guide.pdf.
12. M. Harris, Optimizing Parallel Reduction in CUDA. , 2007 (accessed 27.07.11). http://developer.download.nvidia.com/compute/DevZone/C/html/C/src/reduct ion/doc/reduction.pdf.