Prediction of board-level drop reliability of chip-scale packages with experimental verifications

Proceedings - 2005 International Symposium on Microelectronics, IMAPS 2005

Volumn , Issue , 2005, Pages 586-593

  Yeh, Chang Lin ^a   Lai, Yi Shao ^a   Kao, Chin Li ^a  

^a ADVANCED SEMICONDUCTOR ENGINEERING INC   (Taiwan)

Author keywords

Board level drop test; Consecutive drops; JEDEC; Kinematic hardening; Transient analysis

Indexed keywords

DROP TEST; EXPERIMENTAL OBSERVATION; EXPERIMENTAL VERIFICATION; IMPLICIT TIME INTEGRATION; JEDEC; KINEMATIC HARDENING; SUPPORT EXCITATION SCHEMES; TRANSIENT STRUCTURAL RESPONSE;

HARDENING; KINEMATICS; MICROELECTRONICS; PLASTIC DEFORMATION; STRAIN ENERGY; TRANSIENT ANALYSIS;

DROPS;

EID: 84876948712     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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