Hotspot Preventing Adaptive Routing algorithm for networks-on-chip

International Conference on High Performance Computing, Networking and Communication Systems 2007, HPCNCS 2007

Volumn , Issue , 2007, Pages 171-177

  Bag, Anirban ^a   Bassiouni, Mostafa A ^a  

^a University of Central Florida   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ROUTING; ADAPTIVE ROUTING ALGORITHM; CHIP RELIABILITY; NETWORK TRAFFIC LOADS; NETWORKS ON CHIPS; ON-CHIP COMMUNICATION NETWORKS; SYSTEM ON CHIP DESIGN; TEMPERATURE VARIATION;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMUNICATION SYSTEMS; COMPUTATION THEORY; MICROPROCESSOR CHIPS; ROUTING ALGORITHMS;

NETWORK ROUTING;

EID: 84875692468     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)

1. W. J. Dally. and B. Towles, "Route packets, not wires: onchip interconnection networks", Proceedings of the 38th Conference on Design Automation (Las Vegas, Nevada, United States), DAC '01.
2. G. De Micheli and L. Benini, "Networks on Chip: A New Paradigm for Systems on Chip Design", Proceedings of the Conference on Design, Automation and Test in Europe (March 04 - 08, 2002). Design, Automation, and Test in Europe. IEEE Computer Society, Washington, DC, 418.
3. L. Shang, L. Peh, A. Kumar, and N. K. Jha, "Thermal Modeling, Characterization and Management of On-Chip Networks", Proceedings of the 37th Annual IEEE/ACM international Symposium on Microarchitecture (Portland, Oregon, December 04 - 08, 2004).
4. C. A. Zeferino and A. A. Susin, "SoCIN: A Parametric and Scalable Network-on-Chip", Proceedings of the 16th Symposium on integrated Circuits and Systems Design (September 08 - 11, 2003). SBCCI. IEEE Computer Society, Washington, DC, 169.
5. U. Y. Ogras, J. Hu and R. Marculescu, "Key research problems in NoC design: a holistic perspective", Proceedings of the 3rd IEEE/ACM/IFIP international Conference on Hardware/Software Codesign and System Synthesis (Jersey City, NJ, USA, September 19-21, 2005). CODES+ISSS '05.
6. M. Ali, M. Welzl, M. Zwicknagl and S. Hellebrand, "Considerations for Fault-tolerant Networks on Chips", IEEE ICM'05, Islamabad, Pakistan, 13-15 December 2005.
7. V. Raghunathan, M. B. Srivastava, R. K. Gupta, "A Survey of Techniques for Energy Efficient On-Chip Communication" dac, p. 900, 40th Design Automation Conference (DAC'03), 2003.
8. L. T. Yeh and R. C. Chu, "Thermal Management of Microelectronic Equipment: Heat Transfer Theory, Analysis Methods, and Design Practices." ASME Press, New York, NY, 2002.
9. J. S. Kim, M. B. Taylor, J. Miller, and D. Wentzlaff, "Energy characterization of a tiled architecture processor with on-chip networks", Proc. Int. Symp. Low Power Electronics and Design, pages 424.427, Aug. 2003.
10. K. Skadron et al, "Temperature-aware microarchitecture", Proc. Int. Symp. Computer Architecture, June 2003, pages 1.12.
11. O. Ozturk, F. Wang, M. Kandemir, and Y. Xie, "Optimal topology exploration for application-specific 3D architectures", Proceedings of the 2006 Conference on Asia South Pacific Design Automation (Yokohama, Japan, January 24-27, 2006), ASP-DAC '06.
12. B. Goplen, and S. Sapatnekar, "Thermal via placement in 3D ICs", Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005), ISPD '05.
13. M. Lin, A. El Gamal, Y. Lu and S. Wong, "Performance benefits of monolithically stacked 3D-FPGA", Proceedings of the international Symposium on Field Programmable Gate Arrays (Monterey, California, USA, February 22 - 24, 2006), FPGA'06.
14. J. Cong and Y. Zhang, "Thermal-driven multilevel routing for 3-D ICs", Proceedings of the 2005 Conference on Asia South Pacific Design Automation (Shanghai, China, January 18-21, 2005), ASP-DAC '05.
15. T. Zhang, Y. Zhan and S. S. Sapatnekar, " Temperatureaware routing in 3D ICs", Proceedings of the 2006 Conference on Asia South Pacific Design Automation (Yokohama, Japan, January 24-27, 2006), ASP-DAC '06.
16. C. Tsai and S. Kang, "Standard cell placement for even onchip thermal distribution", Proceedings of the 1999 international Symposium on Physical Design (Monterey, California, United States, April 12 - 14, 1999), ISPD '99.
17. G. M. Link and N. Vijaykrishnan, "Hotspot Prevention through Runtime Reconfiguration in Network-On-Chip", Proceedings of the Conference on Design, Automation and Test in Europe - Volume 1 (March 07 - 11, 2005), Design, Automation, and Test in Europe. IEEE Computer Society, Washington, DC, 648-649.
18. R. Mullins, A. West, and S. Moore, "Low-Latency Virtual- Channel Routers for On-Chip Networks", Proceedings of the 31st Annual international Symposium on Computer Architecture (München, Germany, June 19 - 23, 2004), International Conference on Computer Architecture, IEEE Computer Society, Washington, DC, 188.