Simple 4 G-bit DRAM technology utilizing high-aspect-ratio pillars for cell-capacitors and peripheral-vias simultaneously fabricated

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1997, Pages 29-32

  Nakamura, S ^a   Kosugi, M ^a   Sato, A ^a   Hatada, A ^a   Minakata, H ^a   Kobayashi, M ^a   Kurahashi, T ^a   Suzuki, R ^a   Sasaki, N ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC RANDOM ACCESS MEMORY (DRAM); SALICIDATION;

ASPECT RATIO; CAPACITORS; DIELECTRIC FILMS; ETCHING; INTEGRATED CIRCUIT MANUFACTURE; LEAKAGE CURRENTS; LOW TEMPERATURE OPERATIONS; OXIDATION;

RANDOM ACCESS STORAGE;

EID: 84874889871     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)