-
1
-
-
61549131161
-
3-D hyperintegration and packaging technologies for micronano systems
-
Jan
-
J.-Q. Lu, "3-D hyperintegration and packaging technologies for micronano systems," Proc. IEEE, vol. 97, no. 1, pp. 18-30, Jan. 2009.
-
(2009)
Proc IEEE
, vol.97
, Issue.1
, pp. 18-30
-
-
Lu, J.-Q.1
-
2
-
-
79960901040
-
High-frequency scalable electrical model and analysis of a Through Silicon Via (TSV)
-
Feb.
-
J. Kim, J. S. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, K. Park, S. Yang, M.-S. Suh, K.-Y. Byun, and J. Kim, "High-frequency scalable electrical model and analysis of a Through Silicon Via (TSV)," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 2, pp. 181-195, Feb. 2011.
-
(2011)
IEEE Trans. Compon., Packag., Manuf. Technol
, vol.1
, Issue.2
, pp. 181-195
-
-
Kim, J.1
Pak, J.S.2
Cho, J.3
Song, E.4
Cho, J.5
Kim, H.6
Song, T.7
Lee, J.8
Lee, H.9
Park, K.10
Yang, S.11
Suh, M.-S.12
Byun, K.-Y.13
Kim, J.14
-
3
-
-
80052028414
-
Through-Strata-Via (TSV) parasitics and wideband modeling for three-dimensional integration/packaging
-
Sep.
-
Z. Xu and J.-Q. Lu, "Through-Strata-Via (TSV) parasitics and wideband modeling for three-dimensional integration/packaging," IEEE Electron Device Lett., vol. 32, no. 9, pp. 1278-1280, Sep. 2011.
-
(2011)
IEEE Electron Device Lett
, vol.32
, Issue.9
, pp. 1278-1280
-
-
Xu, Z.1
Lu, J.-Q.2
-
4
-
-
77953026096
-
Through-silicon-via capacitance reduction technique to benefit 3-D IC performance
-
Jun.
-
G. Katti, M. Stucchi, J. V. Olmen, K. D. Meyer, and W. Dehaene, "Through-silicon-via capacitance reduction technique to benefit 3-D IC performance," IEEE Electron Device Lett., vol. 31, no. 6, pp. 549-551, Jun. 2010.
-
(2010)
IEEE Electron Device Lett
, vol.31
, Issue.6
, pp. 549-551
-
-
Katti, G.1
Stucchi, M.2
Olmen, J.V.3
Meyer, K.D.4
Dehaene, W.5
-
5
-
-
84859044803
-
Influence of Bosch etch process on electrical isolation of TSV structures
-
Oct.
-
N. Ranganathan, D. Y. Lee, Y. Liu, G.-Q. Lo, K. Prasad, and K. L. Pey, "Influence of Bosch etch process on electrical isolation of TSV structures," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 10, pp. 1497-1507, Oct. 2011.
-
(2011)
IEEE Trans. Compon., Packag., Manuf. Technol
, vol.1
, Issue.10
, pp. 1497-1507
-
-
Ranganathan, N.1
Lee, D.Y.2
Liu, Y.3
Lo, G.-Q.4
Prasad, K.5
Pey, K.L.6
-
6
-
-
84355166174
-
Processing assessment and adhesion evaluation of copper Through-Silicon Vias (TSVs) for Three-Dimensional Stacked-Integrated Circuit (3D-SIC) architectures
-
Sep.-Nov.
-
Y. Yang, R. Labie, F. Ling, C. Zhao, A. Radisic, J. Van Olmen, Y. Travaly, B. Verlinden, and I. De Wolf, "Processing assessment and adhesion evaluation of copper Through-Silicon Vias (TSVs) for Three-Dimensional Stacked-Integrated Circuit (3D-SIC) architectures," Microelecton. Reliab., vol. 50, no. 9-11, pp. 1636-1640, Sep.-Nov. 2010.
-
(2010)
Microelecton. Reliab
, vol.50
, Issue.9-11
, pp. 1636-1640
-
-
Yang, Y.1
Labie, R.2
Ling, F.3
Zhao, C.4
Radisic, A.5
Van Olmen, J.6
Travaly, Y.7
Verlinden, B.8
De Wolf, I.9
-
7
-
-
79952820386
-
Impact of near-surface thermal stresses on interfacial reliability of through-silicon vias for 3-D interconnects
-
Mar.
-
S.-K. Ryu, K.-H. Lu, X. Zhang, J.-H. Im, P. S. Ho, and R. Huang, "Impact of near-surface thermal stresses on interfacial reliability of through-silicon vias for 3-D interconnects," IEEE Trans. Device Mater. Rel., vol. 11, no. 1, pp. 35-43, Mar. 2011.
-
(2011)
IEEE Trans. Device Mater. Rel
, vol.11
, Issue.1
, pp. 35-43
-
-
Ryu, S.-K.1
Lu, K.-H.2
Zhang, X.3
Im, J.-H.4
Ho, P.S.5
Huang, R.6
-
8
-
-
74649084751
-
Nonlinear thermal stress/strain analyses of copper filled TSV (Through Silicon Via) and their flip-chip microbumps
-
Nov
-
C. S. Selvanayagam, J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. C. Chai, "Nonlinear thermal stress/strain analyses of copper filled TSV (Through Silicon Via) and their flip-chip microbumps," IEEE Trans. Adv. Packag., vol. 32, no. 4, pp. 720-728, Nov. 2009.
-
(2009)
IEEE Trans. Adv. Packag
, vol.32
, Issue.4
, pp. 720-728
-
-
Selvanayagam, C.S.1
Lau, J.H.2
Zhang, X.3
Seah, S.4
Vaidyanathan, K.5
Chai, T.C.6
-
9
-
-
84859803677
-
Modeling stress in silicon with TSVs and its effect on mobility
-
Sep.
-
C. Selvanayagam, X. W. Zhang, R. Rajoo, and D. Pinjala, "Modeling stress in silicon with TSVs and its effect on mobility," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 9, pp. 1328-1335, Sep. 2011.
-
(2011)
IEEE Trans. Compon., Packag., Manuf. Technol
, vol.1
, Issue.9
, pp. 1328-1335
-
-
Selvanayagam, C.1
Zhang, X.W.2
Rajoo, R.3
Pinjala, D.4
-
10
-
-
84859791884
-
3-D wafer-level packaging die stacking using spin-on-dielectric polymer liner throughsilicon vias
-
Jun.
-
Y. Civale, D. S. Tezcan, H. G. G. Philipsen, F. F. C. Duval, P. Jaenen, Y. Travaly, P. Soussan, B. Swinnen, and E. Beyne, "3-D wafer-level packaging die stacking using spin-on-dielectric polymer liner throughsilicon vias," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 6, pp. 833-840, Jun. 2011.
-
(2011)
IEEE Trans. Compon., Packag., Manuf. Technol
, vol.1
, Issue.6
, pp. 833-840
-
-
Civale, Y.1
Tezcan, D.S.2
Philipsen, H.G.G.3
Duval, F.F.C.4
Jaenen, P.5
Travaly, Y.6
Soussan, P.7
Swinnen, B.8
Beyne, E.9
-
11
-
-
84859798579
-
Polymer filling of silicon trenches for 3-D through silicon vias applications
-
Jun.
-
F. F. C. Duval, C. Okoro, Y. Civale, P. Soussan, and E. Beyne, "Polymer filling of silicon trenches for 3-D through silicon vias applications," IEEE Trans. Compon., Packag., Manuf. Technol., vol. 1, no. 6, pp. 825-832, Jun. 2011.
-
(2011)
IEEE Trans. Compon., Packag., Manuf. Technol
, vol.1
, Issue.6
, pp. 825-832
-
-
Duval, F.F.C.1
Okoro, C.2
Civale, Y.3
Soussan, P.4
Beyne, E.5
-
12
-
-
79960398916
-
Reliability study of 3D-WLP through silicon via with innovative polymer filling integration
-
M. Bouchoucha, P. Chausse, S. Moreau, L.-L. Chapelon, N. Sillon, and O. Thomas, "Reliability study of 3D-WLP through silicon via with innovative polymer filling integration," in Proc. IEEE ECTC, 2011, pp. 567-572.
-
(2011)
Proc IEEE ECTC
, pp. 567-572
-
-
Bouchoucha, M.1
Chausse, P.2
Moreau, S.3
Chapelon, L.-L.4
Sillon, N.5
Thomas, O.6
-
13
-
-
77955211800
-
3D interconnection process development and integration with low stress TSV
-
T. T. Chua, S. W. Ho, H. Y. Li, C. H. Khong, E. B Liao, S. P. Chew, W. S. Lee, L. S. Lim, X. F. Pang, S. L. Kriangsak, C. Ng, S. Nathapong, and C. H. Toh, "3D interconnection process development and integration with low stress TSV," in Proc. ECTC, 2010, pp. 798-802.
-
(2010)
Proc. ECTC
, pp. 798-802
-
-
Chua, T.T.1
Ho, S.W.2
Li, H.Y.3
Khong, C.H.4
Liao, E.B.5
Chew, S.P.6
Lee, W.S.7
Lim, L.S.8
Pang, X.F.9
Kriangsak, S.L.10
Ng, C.11
Nathapong, S.12
Toh, C.H.13
-
14
-
-
70349670752
-
Thermomechanical reliability of 3-D ICs containing through silicon vias
-
K. H. Lu, X. Zhang, S.-K. Ryu, J. Im, R. Huang, and P. S. Ho, "Thermomechanical reliability of 3-D ICs containing through silicon vias," in Proc. ECTC, 2009, pp. 630-634.
-
(2009)
Proc. ECTC
, pp. 630-634
-
-
Lu, K.H.1
Zhang, X.2
Ryu, S.-K.3
Im, J.4
Huang, R.5
Ho, P.S.6
-
15
-
-
83755219397
-
Performance evaluation of air-gap-based coaxial RF TSV for 3D NoC
-
L. Yu, H. G. Yang, J. Zhang, and W. Wang, "Performance evaluation of air-gap-based coaxial RF TSV for 3D NoC," in Proc. 19th IEEE Conf. VLSI SOC, 2011, pp. 94-97.
-
(2011)
Proc. 19th IEEE Conf. VLSI SOC
, pp. 94-97
-
-
Yu, L.1
Yang, H.G.2
Zhang, J.3
Wang, W.4
-
16
-
-
0035441452
-
Fabrication of air-channel structures for microfluidic, microelectromechanical, and microelectronic applications
-
DOI 10.1109/84.946793, PII S1057715701050326
-
D. Bhusari, H. A. Reed, M. Wedlake, A. M. Padovani, S. A. B. Allen, and P. A. Kohl, "Fabrication of air-channel structures for microfluidic, microelectromechanical, and microelectronic applications," J. Microelectromech. Syst., vol. 10, no. 3, pp. 400-408, Sep. 2001. (Pubitemid 32981791)
-
(2001)
Journal of Microelectromechanical Systems
, vol.10
, Issue.3
, pp. 400-408
-
-
Bhusari, D.1
Reed, H.A.2
Wedlake, M.3
Padovani, A.M.4
Allen, S.A.B.5
Kohl, P.A.6
-
17
-
-
84874649543
-
Polymer liner formation in high aspect ratio through-silicon-vias for 3D integration
-
to be published, to be published
-
C. Huang, Q. Chen, and Z. Wang, "Polymer liner formation in high aspect ratio through-silicon-vias for 3D integration," IEEE Trans. Compon., Packag., Manuf. Technol., to be published, to be published.
-
IEEE Trans. Compon., Packag., Manuf. Technol.
-
-
Huang, C.1
Chen, Q.2
Wang, Z.3
-
18
-
-
73349133689
-
Electrical modeling and characterization of through silicon via for three-dimensional ICs
-
Jan.
-
G. Katti, M. Stucchi, K. D. Meyer, and W. Dehaene, "Electrical modeling and characterization of through silicon via for three-dimensional ICs," IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 256-262, Jan. 2010.
-
(2010)
IEEE Trans. Electron Devices
, vol.57
, Issue.1
, pp. 256-262
-
-
Katti, G.1
Stucchi, M.2
Meyer, K.D.3
Dehaene, W.4
-
19
-
-
79955536912
-
Achieving stable Through-Silicon Via (TSV) capacitance with oxide fixed charge
-
May
-
L. Zhang, H. Y. Li, S. Gao, and C. S. Tan, "Achieving stable Through-Silicon Via (TSV) capacitance with oxide fixed charge," IEEE Electron Device Lett., vol. 32, no. 5, pp. 668-670, May 2011.
-
(2011)
IEEE Electron Device Lett
, vol.32
, Issue.5
, pp. 668-670
-
-
Zhang, L.1
Li, H.Y.2
Gao, S.3
Tan, C.S.4
-
20
-
-
79959810027
-
Technology assessment of through-silicon via by using C-V and C-t measurements
-
Jul.
-
G. Katti, M. Stucchi, D. Velenis, S. Thangaraju, K. De Meyer, W. Dehaene, and E. Beyne, "Technology assessment of through-silicon via by using C-V and C-t measurements," IEEE Electron Device Lett., vol. 32, no. 7, pp. 946-948, Jul. 2011.
-
(2011)
IEEE Electron Device Lett
, vol.32
, Issue.7
, pp. 946-948
-
-
Katti, G.1
Stucchi, M.2
Velenis, D.3
Thangaraju, S.4
De Meyer, K.5
Dehaene, W.6
Beyne, E.7
-
21
-
-
78650861793
-
Design issues and considerations for low-cost 3-D TSV IC technology
-
Jan.
-
G. V. Plas, P. Limaye, I. Loi, A. Mercha, H. Oprins, C. Torregiani, S. Thijs, D. Linten, M. Stucchi, G. Katti, D. Velenis, V. Cherman, B. Vandevelde, V. Simons, I. De Wolf, R. Labie, D. Perry, S. Bronckers, N. Minas, M. Cupac, W. Ruythooren, J. Van Olmen, A. Phommahaxay, M. de Potter de ten Broeck, A. Opdebeeck, M. Rakowski, B. De Wachter, M. Dehan, M. Nelis, R. Agarwal, A. Pullini, F. Angiolini, L. Benini, W. Dehaene, Y. Travaly, E. Beyne, and P. Marchal, "Design issues and considerations for low-cost 3-D TSV IC technology," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 293-307, Jan. 2011.
-
(2011)
IEEE J. Solid-State Circuits
, vol.46
, Issue.1
, pp. 293-307
-
-
Plas, G.V.1
Limaye, P.2
Loi, I.3
Mercha, A.4
Oprins, H.5
Torregiani, C.6
Thijs, S.7
Linten, D.8
Stucchi, M.9
Katti, G.10
Velenis, D.11
Cherman, V.12
Vandevelde, B.13
Simons, V.14
De Wolf, I.15
Labie, R.16
Perry, D.17
Bronckers, S.18
Minas, N.19
Cupac, M.20
Ruythooren, W.21
Van Olmen, J.22
Phommahaxay, A.23
Broeck Ten De Potter, M.D.24
Opdebeeck, A.25
Rakowski, M.26
De Wachter, B.27
Dehan, M.28
Nelis, M.29
Agarwal, R.30
Pullini, A.31
Angiolini, F.32
Benini, L.33
Dehaene, W.34
Travaly, Y.35
Beyne, E.36
Marchal, P.37
more..
-
22
-
-
78649449630
-
Three-dimensional chip stack with integrated decoupling capacitors and thru-Si via interconnects
-
Dec.
-
B. Dang, M. Shapiro, P. Andry, C. Tsang, E. Sprogis, S. Wright, M. Interrante, J. Griffith, V. Truong, L. Guerin, R. Liptak, D. Berger, and J. Knickerbocker, "Three-dimensional chip stack with integrated decoupling capacitors and thru-Si via interconnects," IEEE Electron Device Lett., vol. 31, no. 12, pp. 1461-1463, Dec. 2010.
-
(2010)
IEEE Electron Device Lett
, vol.31
, Issue.12
, pp. 1461-1463
-
-
Dang, B.1
Shapiro, M.2
Andry, P.3
Tsang, C.4
Sprogis, E.5
Wright, S.6
Interrante, M.7
Griffith, J.8
Truong, V.9
Guerin, L.10
Liptak, R.11
Berger, D.12
Knickerbocker, J.13
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