Germanium-tin (GeSn) p-channel MOSFETs fabricated on (100) and (111) surface orientations with Sub-400 °cSi2H6 passivation

IEEE Electron Device Letters

Volumn 34, Issue 3, 2013, Pages 339-341

  Gong, Xiao ^a   Han, Genquan ^a   Bai, Fan ^a   Su, Shaojian ^b   Guo, Pengfei ^a   Yang, Yue ^a   Cheng, Ran ^a   Zhang, Dongliang ^c   Zhang, Guangze ^c   Xue, Chunlai ^c   Cheng, Buwen ^c   Pan, Jisheng ^a,d   Zhang, Zheng ^d   Tok, Eng Soon ^a   Antoniadis, Dimitri ^e   Yeo, Yee Chia ^a  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b HUAQIAO UNIVERSITY   (China)

^c INSTITUTE OF SEMICONDUCTORS   (China)

^d INSTITUTE OF MATERIALS RESEARCH AND ENGINEERING   (Singapore)

^e Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

(100) and (111) surface orientations; GeSn p channel metal oxide semiconductor field effect transistors (pMOSFETs); Si2H6 passivation

Indexed keywords

DRIVE CURRENTS; GATE STACK FORMATION; GE SUBSTRATES; METAL-OXIDE; METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR; MOSFETS; P CHANNELS; P-MOSFETS; SOURCE/DRAIN SERIES RESISTANCES; STRAINED-GE; SUBTHRESHOLD SWING; SURFACE ORIENTATION; V AND V;

ELECTRIC RESISTANCE; GERMANIUM; PASSIVATION; TIN;

MOSFET DEVICES;

EID: 84874651454     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2012.2236880     Document Type: Article

References (19)

1. P. Zimmerman, G. Nicholas, B. De Jaeger, B. Kaczer, A. Stesmans, L.-Å. Ragnarsson, D. P. Brunco, F. E. Leys, M. Caymax, G. Winderickx, K. Opsomer, M. Meuris, and M. M. Heyns, "High performance Ge pMOS devices using a Si-compatible process flow," in Proc. IEDM, 2006, pp. 26.1.1-26.1.4.
2. K. H. Kim, R. G. Gordon, A. Ritenour, and D. A. Antoniadis, "Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-k oxide/tungsten nitride gate stacks," Appl. Phys. Lett., vol. 90, no. 21, pp. 212104-1-212104-3, May 2007.
3. G. Nicholas, D. P. Brunco, A. Dimoulas, J. V. Steenbergen, F. Bellenger, M. Houssa,M. Caymax, M. Meuris, Y. Panayiotatos, and A. Sotiropoulos, "Germanium MOSFETs with GeO2/HfO2/TiN gate stacks," IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1425-1430, Jun. 2007. (Pubitemid 46876263)
4. H. Matsubara, T. Sasada, M. Takenaka, and S. Takagi, "Evidence of low interface trap density in GeO2/Ge metal-oxide-semiconductor structures fabricated by thermal oxidation," Appl. Phys. Lett., vol. 93, no. 3, pp. 032104-1-032104-3, Jul. 2008.
5. T. Takahashi, T. Nishimura, L. Chen, S. Sakata, K. Kita, and A. Toriumi, "Proof of Ge-interfacing concepts for metal/high-k/Ge CMOS: Geintimate material selection and interface conscious process flow," in Proc. IEDM, 2007, pp. 697-700.
6. R. Pillarisetty, B. Chu-Kung, S. Corcoran, G. Dewey, J. Kavalieros, H. Kennel, R. Kotlyar, V. Le, D. Lionberger, M. Metz, N. Mukherjee, J. Nah, W. Rachmady, M. Radosavljevic, U. Shah, S. Taft, H. Then, N. Zelick, and R. Chau, "High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (VCC = 0.5 V) III-V CMOS architecture," in Proc. IEDM, 2010, pp. 150-153.
7. L. Hutin, C. Le Royer, J. F. Damlencourt, J. M. Hartmann, H. Grampeix, V. Mazzocchi, C. Tabone, B. Previtali, A. Pouydebasque, M. Vinet, and O. Faynot, "GeOI pMOSFETs scaled down to 30-nm gate length with record off-state current," IEEE Electron Device Lett., vol. 31, no. 3, pp. 234-236, Mar. 2010.
8. P. Hashemi, W. Chern, H. Lee, J. T. Teherani, Y. Zhu, J. Gonsalvez, G. G. Shahidi, and J. L. Hoyt, "Ultrathin strained-Ge channel p-MOSFETs with high-k/metal gate and sub-1-nm equivalent oxide thickness," IEEE Electron Device Lett., vol. 33, no. 7, pp. 943-945, Jul. 2012.
9. B. Liu,X.Gong, G. Han, P. S.Y. Lim,Y. Tong, Q. Zhou,Y.Yang, N. Daval, C. Veytizou, D. Delprat, B.-Y. Nguyen, and Y.-C. Yeo, "High performance germanium Ω-gate MuGFET with Schottky-barrier nickel germanide source/drain and low temperature disilane passivated gate stack," IEEE Electron Device Lett., vol. 33, no. 10, pp. 1336-1338, Oct. 2012.
10. G. Han, S. Su, C. Zhan, Q. Zhou, Y. Yang, L. Wang, P. Guo, W. Wang, C. P. Wong, Z. X. Shen, B. Cheng, and Y.-C. Yeo, "Highmobility germanium-tin (GeSn) p-channel MOSFETs featuring metallic source/drain and sub-370 ?C process modules," in Proc. IEDM, 2011, pp. 402-406.
11. S. Gupta, R. Chen, B. Magyari-Kope, H. Lin, B. Yang, A. Nainani, Y. Nishi, J. S. Harris, and K. C. Saraswat, "GeSn technology: Extending the Ge electronics roadmap," in Proc. IEDM, 2011, pp. 398-401.
12. A. Teramoto, T. Hamada, M. Yamamoto, P. Gaubert, H. Akahori, K. Nii, M. Hirayama, K. Arima, K. Endo, S. Sugawa, and H. Ohmi, "Very high carrier mobility for high-performance CMOS on a Si(110) surface," IEEE Trans. Electron Devices, vol. 54, no. 6, pp. 1438-1445, Jun. 2007. (Pubitemid 46864778)
13. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's-Part II: Effects of surface orientation," IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2363-2368, Dec. 1994.
14. H. S. Momose, T. Ohguro, S. Nakamura, Y. Toyoshima, H. Ishiuchi, and H. Iwai, "Ultrathin gate oxide CMOS on (111) surface-oriented Si substrate," IEEE Trans. Electron Devices, vol. 49, no. 9, pp. 1597-1605, Sep. 2002. (Pubitemid 35017146)
15. D. Kuzum, A. J. Pethe, T. Krishnamohan, Y. Oshima, Y. Sun, J. P. McVittie, P. A. Pianetta, P. C. McIntyre, and K. C. Saraswat, "Interfaceengineered Ge (100) and (111) n-and p-FETs with high mobility," in Proc. IEDM, 2007, pp. 723-726.
16. Y.-J. Yang, W. S. Ho, C.-F. Huang, S. T. Chang, and C. W. Liu, "Electron mobility enhancement in strained-germanium n-channel metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 91, no. 10, pp. 102103-1-102103-3, Sep. 2007.
17. G. Han, S. Su, Q. Zhou, P. Guo, Y. Yang, C. Zhan, L. Wang, W. Wang, Q. Wang, C. Xue, B. Cheng, and Y.-C. Yeo, "Dopant segregation and nickel stanogermanide contact formation on p+ Ge0.947Sn0.053 source/drain," IEEE Electron Device Lett., vol. 33, no. 5, pp. 634-636, May 2012.
18. G. Niu, J. Cressler, S. Mathew, and S. Subbanna, "A total resistance slope based effective channel mobility extraction method for deep submicrometer CMOS technology," IEEE Trans. Electron Devices, vol. 46, no. 9, pp. 1912-1914, Sep. 1999.
19. C. Riddet, J. R. Watling, K. Chan, E. H. C. Parker, T. E. Whall, D. R. Leadley, and A. Asenov, "Hole mobility in germanium as a function of substrate and channel orientation, strain, doping, and temperature," IEEE Trans. Electron Devices, vol. 59, no. 7, pp. 1878-1884, Jul. 2012.