Hardware-efficient EVD processor architecture in FastICA for epileptic seizure detection

2012 Conference Handbook - Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2012

Volumn , Issue , 2012, Pages

  Shih, Yi Hsin ^a   Chen, Tsan Jieh ^a   Yang, Chia Hsiang ^a   Chiueh, Herming ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

AREA REDUCTION; ARRAY STRUCTURES; CO-ORDINATE ROTATION DIGITAL COMPUTERS; CONVERGENCE TIME; CRITICAL PATHS; DETECTION ACCURACY; EIGENVALUE DECOMPOSITION; EPILEPTIC SEIZURE DETECTION; EPILEPTIC SEIZURES; FAST-ICA; GIVENS ROTATION; HARDWARE ARCHITECTURE; HARDWARE REDUCTION; HUMAN ELECTROENCEPHALOGRAM; INDEPENDENT COMPONENT ANALYSIS(ICA); ITERATIVE CALCULATION; JACOBI METHODS; MATHEMATICAL FORMULATION; MULTI-CHANNEL; NUMBER OF ITERATIONS; PRE-PROCESSING; PROCESSING CYCLES; PROCESSING ELEMENTS; PROCESSOR ARCHITECTURES; ROTATION ANGLES; SEIZURE DETECTION; SEIZURE PREDICTION; SIGNAL PROCESSING TECHNIQUE; TRIGONOMETRIC FUNCTIONS;

ALGORITHMS; COMPUTER ARCHITECTURE; DATA PROCESSING; EIGENVALUES AND EIGENFUNCTIONS; ELECTROENCEPHALOGRAPHY; HARDWARE; INDEPENDENT COMPONENT ANALYSIS; ITERATIVE METHODS; NEUROPHYSIOLOGY; TABLE LOOKUP;

SIGNAL DETECTION;

EID: 84874430574     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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