A runtime framework for energy efficient HPC systems without a priori knowledge of applications

Proceedings of the International Conference on Parallel and Distributed Systems - ICPADS

Volumn , Issue , 2012, Pages 660-667

  Chetsa, Ghislain Landry Tsafack ^a   Lefevre, Laurent ^a   Pierson, Jean Marc ^b   Stolf, Patricia ^b   Da Costa, Georges ^b  

^a UNIVERSITÉ DE LYON   (France)

^b UNIVERSITÉ DE TOULOUSE   (France)

Author keywords

Energy efficiency; Execution vector; Green leverage; Phase recognition

Indexed keywords

COMPUTING DEMANDS; DYNAMIC MANAGEMENT; ENERGY EFFICIENT; GREEN LEVERAGE; HIGH PERFORMANCE COMPUTING SYSTEMS; ON-THE-FLY; PEAK PERFORMANCE; PERFORMANCE DEGRADATION; PHASE DETECTION; PHASE RECOGNITION; PRIORI KNOWLEDGE; RESOURCE DEMANDS; RUNTIME FRAMEWORKS;

COMPUTER SYSTEMS; ENERGY EFFICIENCY;

POWER QUALITY;

EID: 84874073126     PISSN: 15219097     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPADS.2012.94     Document Type: Conference Paper

References (13)

1. Rountree B, Lowenthal D, Supinski B, Schulz M, Freeh V, Bletsch T, "Adagio: making DVS practical for complex HPC applications," Proceedings of the 23th International Conference on Supercomputing (ICS09), Yorktown Heights, New York, USA. 812 Jun., 2009, pp. 460-469.
2. Kappiah N, Freeh V, Lowenthal D, "Just in time dynamic voltage scaling: exploiting inter-node slack to save energy in mpi programs," Proceedings of the 19th ACM/IEEE Conference on Supercomputing (SC05), Washington, USA. 12-18 Nov., 2005, pp. 33-41.
3. R. Kotla, A. Devgan, S. Ghiasi, T. Keller and F. Rawson, "Characterizing the Impact of Different Memory-Intensity Levels," IEEE 7th AnnualWorkshop onWorkload Characterization (WWC-7), Oct. 2004.
4. C. Isci, G. Contreras, and M. Martonosi, "Live, runtime phase monitoring and prediction on real systems with application to dynamic power management," Proc. MICRO, 2006, pp. 359370.
5. K. Choi, R. Soma, and M. Pedram, "Fine-grained dynamic voltage and frequency scaling for precise energy and performance tradeoff based on the ratio of off-chip access to onchip computation times," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 1, pp. 1828, Jan. 2005.
6. Lim M, Freeh V, Lowenthal D, "Adaptive, transparent frequency and voltage scaling of communication phases in mpi programs," in proceedings of the 20th ACM/IEEE Conference on Supercomputing (SC06), Tampa, Florida, USA. 11-17 Nov., 2006, pp. 14-27.
7. G.L. Tsafack, L. Lefevre, J.M. Pierson, P. Stolf, and G.D. Costa, "DNA-inspired Scheme for Building the Energy Profile of HPC Systems," In proceedings of the First International Workshop on Energy-Efficient Data Centres, Madrid, Spain, May 2012.
8. G. Contreras, "Power prediction for intel xscale processors using performance monitoring unit events," In proceedings of the International symposium on Low power electronics and design (ISLPED, ACM Press, 2005, pp. 221226.
9. K. Singh, M. Bhadauria, and S. A. McKee, "Real time power estimation and thread scheduling via performance counters," SIGARCH Comput. Archit. News, 37:4655, July 2009.
10. D. H. Bailey, E. Barszcz, J. T. Barton, R. L. Carter, T .A. Lasinski, D. S. Browning, L. Dagum, R. A. Fatoohi, P. O. Frederickson, and R. S. Schreiber, "The nas parallel benchmarks. International Journal of High Performance Computing Applications," 1991, 5:6373.
11. C. Isci and M. Martonosi. Identifying program power phase behavior using power vectors, "In Workshop on Workload Characterization," September 2003.
12. T. Sherwood, E. Perelman, G. Hamerly and B. Calder, "Automatically Characterizing Large Scale Program Behavior," Proceedings of the Tenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS X), Oct., 2002, pp 45-57.
13. W. C. Skamarock, J. B. Klemp, J. Dudhia, D. Gill, D. Barker, W. Wang, J. G. Powers, "A description of the Advanced Research WRF Version 2. NCAR Technical Note," NCAR/TN-468+STR (2005).