A memory-efficient parallel single pass architecture for connected component labeling of streamed images

FPT 2012 - 2012 International Conference on Field-Programmable Technology

Volumn , Issue , 2012, Pages 159-165

  Klaiber, Michael ^a   Rockstroh, Lars ^a   Wang, Zhe ^a   Baroud, Yousef ^a   Simon, Sven ^a  

^a UNIVERSITY OF STUTTGART   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CLOCK CYCLES; CONNECTED COMPONENT LABELING; CONNECTED COMPONENT LABELING ALGORITHM; EFFICIENT IMPLEMENTATION; EXTERNAL MEMORY; HARDWARE ARCHITECTURE; HARDWARE RESOURCES; HIGH BANDWIDTH; HIGH THROUGHPUT; IMAGE STREAMS; MEMORY REDUCTION; MEMORY REQUIREMENTS; PARALLEL-CONNECTED; SINGLE IMAGES; SINGLE PASS; SINGLE-PASS ALGORITHM;

ALGORITHMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; IMAGE PROCESSING;

MEMORY ARCHITECTURE;

EID: 84874038322     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPT.2012.6412129     Document Type: Conference Paper

References (8)

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