Apple-CORE: Microgrids of SVP cores - Flexible, general-purpose, fine-grained hardware concurrency management

Proceedings - 15th Euromicro Conference on Digital System Design, DSD 2012

Volumn , Issue , 2012, Pages 501-508

  Poss, Raphael ^a   Lankamp, Mike ^a   Yang, Qiang ^a   Fu, Jian ^a   Van Tol, Michiel W ^a   Jesshope, Chris ^a  

^a UNIVERSITY OF AMSTERDAM   (Netherlands)

Author keywords

concurrency; hardware multithreading; many core; microthreads; multi core; parallel programming

Indexed keywords

CONCURRENCY; HARDWARE MULTITHREADING; MANY-CORE; MICROTHREADS; MULTI CORE;

CACHE MEMORY; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; CONCURRENCY CONTROL; FRUITS; GENERAL PURPOSE COMPUTERS; HARDWARE; MICROPROCESSOR CHIPS; MODEL CHECKING; MULTITASKING; PARALLEL PROGRAMMING; SYSTEMS ANALYSIS;

COMPUTER VISION;

EID: 84872917614     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2012.25     Document Type: Conference Paper

References (42)

1. R. Ronen, A. Mendelson, K. Lai, S.-L. Lu, F. Pollack, and J. Shen, "Coming challenges in microarchitecture and architecture," Proceedings of the IEEE, vol. 89, no. 3, pp. 325-340, mar 2001.
2. L. Spracklen and S. G. Abraham, "Chip multithreading: opportunities and challenges," in Proc 11th International Symposium on High-Performance Computer Architecture, ser. HPCA'05. IEEE, February 2005, pp. 248-252.
3. H. Sutter, "The free lunch is over: A fundamental turn toward concurrency in software," Dr. Dobb's Journal, vol. 30, no. 3, 2005.
4. M. Shah, R. Golla, P. Jordan, G. Grohoski, J. Barreh, J. Brooks, M. Greenberg, G. Levinsky, M. Luttrell, C. Olson, Z. Samoail, M. Smittle, and T. Ziaja, "SPARC T4: A dynamically threaded server-on-a-chip," IEEE Micro, vol. PP, no. 99, p. 1, 2012.
5. Advanced Micro Devices, Inc., "AMD Fusion APU era begins." [Online]. Available: http://www.amd.com/us/press-releases/Pages/amd-fusion-apu- era-2011jan04.aspx
6. S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani, "A network on chip architecture and design methodology," in Proc. IEEE Computer Society Annual Symposium on VLSI, 2002, pp. 105-112.
7. J. Henkel, W. Wolf, and S. Chakradhar, "On-chip networks: a scalable, communication-centric embedded system design paradigm," in Proc. 17th International Conference on VLSI Design, 2004, pp. 845-851.
8. O. Moreira, J. J.-D. Mol, and M. Bekooij, "Online resource management in a multiprocessor with a network-on-chip," in Proc. 2007 ACM symposium on Applied computing, ser. SAC '07. ACM, 2007, pp. 1557-1564.
9. W. A. Wulf and S. A. McKee, "Hitting the memory wall: implications of the obvious," SIGARCH Comput. Archit. News, vol. 23, pp. 20-24, March 1995.
10. I. Bell, N. Hasasneh, and C. Jesshope, "Supporting microthread scheduling and synchronisation in CMPs," International Journal of Parallel Programming, vol. 34, pp. 343-381, 2006.
11. J. E. Thornton, "Parallel operation in the Control Data 6600," in Proceedings of the October 27-29, 1964, fall joint computer conference, part II: very high speed computer systems, ser. AFIPS '64 (Fall, part II). New York, NY, USA: ACM, 1965, pp. 33-40.
12. B. Smith, "Architecture and applications of the HEP multiprocessor computer system," Proc. SPIE Int. Soc. Opt. Eng.; (United States), vol. 298, pp. 241-248, 1981.
13. J. Boisseau, L. Carter, A. Snavely, D. Callahan, J. Feo, S. Kahan, and Z. Wu, "CRAY T90 vs. Tera MTA: The old champ faces a new challenger," in Proc. Cray User's Group Conference. 411 First Avenue South, Seattle, WA 9810, USA: Cray Inc., June 1998.
14. A. Snavely, L. Carter, J. Boisseau, A. Majumdar, K. S. Gatlin, N. Mitchell, J. Feo, and B. Koblenz, "Multi-processor performance on the Tera MTA," in Supercomputing '98: Proceedings of the 1998 ACM/IEEE conference on Supercomputing. Washington, DC, USA: IEEE Computer Society, 1998, pp. 1-8.
15. D. M. Tullsen, S. J. Eggers, and H. M. Levy, "Simultaneous multithreading: maximizing on-chip parallelism," SIGARCH Comput. Archit. News, vol. 23, pp. 392-403, May 1995.
16. D. T. Marr, F. Binns, D. L. Hill, G. Hinton, D. A. Koufaty, J. A. Miller, and M. Upton, "Hyper-Threading technology architecture and microarchitecture," Intel Technology Journal, vol. 6, no. 1, pp. 1-12, 2002. [Online]. Available: http://www.mendeley.com/research/hyperthreading- technology-architecture-and-microarchitecture/
17. R. H. Halstead, Jr. and T. Fujita, "MASA: a multithreaded processor architecture for parallel symbolic computing," SIGARCH Comput. Archit. News, vol. 16, pp. 443-451, May 1988. [Online]. Available: 10.1145/633625.52449
18. R. S. Nikhil and Arvind, "Can dataflow subsume von Neumann computing?" SIGARCH Comput. Archit. News, vol. 17, no. 3, pp. 262-272, 1989.
19. D. May and R. Shepherd, "Occam and the transputer," in Advances in Petri Nets 1989, ser. Lecture Notes in Computer Science. Springer Berlin / Heidelberg, 1990, vol. 424, pp. 329-353.
20. D. E. Culler, A. Sah, K. E. Schauser, T. von Eicken, and J. Wawrzynek, "Fine-grain parallelism with minimal hardware support: a compiler-controlled threaded abstract machine," in ASPLOS-IV: Proc. 4th international conference on Architectural support for programming languages and operating systems. New York, NY, USA: ACM, 1991, pp. 164-175.
21. T. Anderson, E. Lazowska, and H. Levy, "The performance implications of thread management alternatives for shared-memory multiprocessors," IEEE Trans. Comput., vol. 38, no. 12, pp. 1631-1644, dec 1989.
22. L. Zhang and C. R. Jesshope, "On-Chip COMA Cache-Coherence Protocol for Microgrids of Microthreaded Cores," in Euro-Par Workshops, ser. LNCS, Bouge and et al., Eds., vol. 4854. Springer, 2007, pp. 38-48.
23. T. D.Vu, L. Zhang, and C. R. Jesshope, "The verification of the on-chip COMA cache coherence protocol," in International Conference on Algebraic Methodology and Software Technology, 2008, pp. 413-429.
24. L. G. Valiant, "A bridging model for parallel computation," Commun. ACM, vol. 33, pp. 103-111, aug. 1990.
25. OpenMP Architecture Review Board. (2008) OpenMP application program interface, version 3.0. [Online]. Available: http://www.openmp.org/mp-documents/ spec30.pdf
26. Khronos OpenCL Working Group. (2009) The OpenCL specification, version 1.0.43.
27. C. E. Leiserson, "The Cilk++ concurrency platform," in DAC '09: Proceedings of the 46th Annual Design Automation Conference. New York, NY, USA: ACM, 2009, pp. 522-527.
28. R. E. Ladner and M. J. Fischer, "Parallel prefix computation," J. ACM, vol. 27, no. 4, pp. 831-838, October 1980.
29. E. W. Dijkstra, "Hierarchical ordering of sequential processes," Acta Informatica, vol. 1, no. 2, pp. 115-138, June 1971.
30. R. Poss, M. Lankamp, M. I. Uddin, J. Sýkora, and L. Kafka, "Heterogeneous integration to simplify many-core architecture simulations," in Proc. 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, ser. RAPIDO '12. ACM, 2012, pp. 17-24.
31. M. A. Hicks, M. W. van Tol, and C. R. Jesshope, "Towards Scalable I/O on a Many-core Architecture," in International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS). IEEE, July 2010, pp. 341-348.
32. S. Wilton and N. Jouppi, "Cacti: an enhanced cache access and cycle time model," Solid-State Circuits, IEEE Journal of, vol. 31, no. 5, pp. 677-688, may 1996.
33. M. K. McKusick and G. V. Neville-Neil, Design And Implementation Of The FreeBSD Operating System. Addison Wesley, 2004.
34. M. W. van Tol and C. R. Jesshope, "An operating system strategy for general-purpose parallel computing on many-core architectures," Advances in Parallel Computing, vol. High Performance Computing: From Grids and Clouds to Exascale, no. 20, pp. 157-181, 2011.
35. J. S. Chase, H. M. Levy, M. J. Feeley, and E. D. Lazowska, "Sharing and protection in a single-address-space operating system," ACM Trans. Comput. Syst., vol. 12, pp. 271-307, November 1994.
36. D. Saougkos, D. Evgenidou, and G. Manis, "Specifying loop transformations for C2μTC source-ro-source compiler," in Proc. of 14th Workshop on Compilers for Parallel Computing (CPC'09), Zürich, Switzerland. IBM Research Center, January 2009.
37. D. Saougkos and G. Manis, "Run-time scheduling with the C2uTC parallelizing compiler," in 2nd Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures, in Workshop Proceedings of the 24th Conference on Computing Systems (ARCS 2011), ser. Lecture Notes in Computer Science. Springer, 2011, pp. 151-157.
38. C. Grelck and S.-B. Scholz, "SAC: a functional array language for efficient multi-threaded execution," International Journal of Parallel Programming, vol. 34, no. 4, pp. 383-427, Aug 2006.
39. C. Grelck, S. Herhut, C. Jesshope, C. Joslin, M. Lankamp, S.-B. Scholz, and A. Shafarenko, "Compiling the Functional Data-Parallel Language SaC for Microgrids of Self-Adaptive Virtual Processors," in 14th Workshop on Compilers for Parallel Computing (CPC'09), IBM Research Center, Zurich, Switzerland, 2009.
40. Z. Tan, C. Lin, H. Yin, and B. Li, "Optimization and benchmark of cryptographic algorithms on network processors," IEEE Micro, vol. 24, no. 5, pp. 55-69, September/October 2004.
41. Y. Yue, C. Lin, and Z. Tan, "NPCryptBench: a cryptographic benchmark suite for network processors," SIGARCH Comput. Archit. News, vol. 34, no. 1, pp. 49-56, September 2005.
42. M. Ferdman, A. Adileh, O. Kocberber, S. Volos, M. Alisafaee, D. Jevdjic, C. Kaynak, A. D. Popescu, A. Ailamaki, and B. Falsafi, "Clearing the clouds: a study of emerging scale-out workloads on modern hardware," in Proc. 17th international conference on Architectural Support for Programming Languages and Operating Systems, ser. ASPLOS '12. ACM, 2012, pp. 37-48.