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Volumn 18, Issue 1, 2010, Pages 47-58

FastCrypto: Parallel AES pipelines extension for general-purpose processors

Author keywords

AES pipeline; Cryptography; Decoupled architectures; FPGA implementation; Parallel processing

Indexed keywords


EID: 84872874461     PISSN: 10615369     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (1)

References (24)
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  • 4
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    • Advanced Encryption Standard (AES), US National Institute of Standards and Technology
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  • 7
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    • Design and performance testing of a 2.29 Gb/s rijndael processor
    • I. Verbauwhede, P. Schaumont, and H. Kuo, " Design and performance testing of a 2.29 Gb/s rijndael processor," IEEE Journal of Solid-State Circuits, Vol. 38, No.3, pp. 569-572, 2003.
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    • Verbauwhede, I.1    Schaumont, P.2    Kuo, H.3
  • 10
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    • Area-throughput trade-offs for fully pipelined 30 to 70 gbits/s AES processors
    • A. Hodjat and I. Verbauwhede, " Area-throughput trade-offs for fully pipelined 30 to 70 gbits/s AES processors," IEEE Transactions on Computers, Vol. 55, No. 4, pp. 366-372, 2006.
    • (2006) IEEE Transactions on Computers , vol.55 , Issue.4 , pp. 366-372
    • Hodjat, A.1    Verbauwhede, I.2
  • 12
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    • An FPGA-based performance evaluation of the AES block cipher candidate algorithm finalists
    • DOI 10.1109/92.931230, PII S1063821001032966
    • A. Elbirt, W. Yip, B. Chetwynd, and C. Paar, "An FPGA Based Performance Evaluation of the AES Block Cipher Candidate Algorithm Finalists," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 4, pp. 545-557, 2001. (Pubitemid 32680577)
    • (2001) IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.9 , Issue.4 , pp. 545-557
    • Elbirt, A.J.1    Yip, W.2    Chetwynd, B.3    Paar, C.4
  • 13
    • 84937540201 scopus 로고    scopus 로고
    • Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays
    • San Francisco, CA, USA, LNCS2020, ISBN 3-540-41898-9
    • K. Gaj and P. Chodowiec, " Fast implementation and fair comparison of the final candidates for advanced encryption standard using field programmable gate arrays," Proc. 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA (CT-RSA2001), San Francisco, CA, USA, LNCS2020, ISBN 3-540-41898-9, pp. 84-99, 2001.
    • (2001) Proc. 2001 Conference on Topics in Cryptology: The Cryptographer's Track at RSA (CT-RSA2001) , pp. 84-99
    • Gaj, K.1    Chodowiec, P.2
  • 17
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    • Decoupled access/execute computer architectures
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    • Smith, J.1
  • 18
    • 84872852296 scopus 로고    scopus 로고
    • MIPS32 Architecture For Programmers
    • MIPS32 Architecture For Programmers, Volume I: Introduction to the MIPS32 Architecture, Available at http://www.rnips.com/products/productmaterials/ processor/mips-architecture/, 2008.
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  • 22
    • 35248847435 scopus 로고    scopus 로고
    • Efficient implementation of rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs
    • Cologne, Germany, LNCS2779, ISBN 3-540-40833-9
    • F. Standaert, G. Rouvroy, J. Quisquater, and J. Legat, " Efficient implementation of rijndael encryption in reconfigurable hardware: Improvements and design tradeoffs," Proc. Cryptographic Hardware and Embedded Systems (CHES2003), Cologne, Germany, LNCS2779, ISBN 3-540-40833-9, pp. 334-350, 2003.
    • (2003) Proc. Cryptographic Hardware and Embedded Systems (CHES2003) , pp. 334-350
    • Standaert, F.1    Rouvroy, G.2    Quisquater, J.3    Legat, J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.