A low-voltage 1 Mb FRAM in 0.13 m CMOS featuring time-to-digital sensing for expanded operating margin

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 1, 2012, Pages 141-150

  Qazi, Masood ^a   Clinton, Michael ^b   Bartling, Steven ^b   Chandrakasan, Anantha P ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^b TEXAS INSTRUMENTS   (United States)

Author keywords

Analog to digital conversion; CMOS memory circuits; FeRAM; FRAM; low power electronics; nonvolatile memory; offset compensation; random access memory; storage class memory; time to digital conversion; voltage scaling

Indexed keywords

CMOS MEMORY CIRCUITS; FERAM; FRAM; NON-VOLATILE MEMORY; OFFSET COMPENSATION; RANDOM ACCESS MEMORY; STORAGE-CLASS MEMORY; TIME-TO-DIGITAL CONVERSIONS; VOLTAGE-SCALING;

DATA STORAGE EQUIPMENT; DIGITAL CIRCUITS; LOW POWER ELECTRONICS; NONVOLATILE STORAGE; POWER ELECTRONICS; RANDOM ACCESS STORAGE;

FERROELECTRIC DEVICES;

EID: 84872866440     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2164732     Document Type: Article

References (24)

1. S. Henzler, S. Koeppe, D. Lorenz, W. Kamp, R. Kuenemund, and D. Schmitt-Landsiedel, "A local passive time interpolation concept for variation-tolerant high-resolution time-to-digital conversion," IEEE J. Solid-State Circuits, vol. 43, no. 7, pp. 1666-1676, 2008.
2. J. Kwong, Y. K. Ramadass, N. Verma, and A. P. Chandrakasan, "A 65 nm sub-Vt microcontroller with integrated SRAMand switched capacitor DC-DC converter," IEEE J. Solid-State Circuits, vol. 44, no. 1, pp. 115-126, 2009.
3. G. Chen, M. Fojtik, D. Kim, D. Fick, J. Park, M. Seok, M.-T. Chen, Z. Foo, D. Sylvester, and D. Blaauw, "Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells," in IEEE Int. Solid-State Circuits Conf. Dig., 2010, pp. 288-289.
4. M. Zwerg, A. Baumann, R. Kuhn, M. Arnold, R. Nerlich,M. Herzog, R. Ledwa, C. Sichert, V. Rzehak, P. Thanigai, and B. O. Eversmann, "An 82 microcontroller with embedded FeRAM for energyharvesting applications," in IEEE Int. Solid-State Circuits Conf. Dig., 2011, pp. 334-335.
5. T. S. Moise, S. R. Summerfelt, H. McAdams, S. Aggarwal, K. R. Udayakumar, F. G. Celii, J. S. Martin, G. Xing, L. Hall, K. J. Taylor, T. Hurd, J. Rodriguez, K. Remack, M. D. Khan, K. Boku, G. Stacey, M. Yao, M. G. Albrecht, E. Zielinski, M. Thakre, S. Kuchimanchi, A. Thomas, B. McKee, J. Rickes, A. Wang, J. Grace, J. Fong, D. Lee, C. Pietrzyk, R. Lanham, S. R. Gilbert, D. Taylor, J. Amano, R. Bailey, F. Chu, G. Fox, S. Sun, and T. Davenport, "Demonstration of a 4 Mb, high density ferroelectric memory embedded within a 130 nm, 5 LM Cu/FSG logic process," in Proc. IEEE Int. Electron Devices Meeting, 2002, pp. 535-538.
6. D. Takashima, H. Shiga, D. Hashimoto, T. Miyakawa, S. Shiratake, K. Hoya, R. Ogiwara, R. Takizawa, S. Doumae, R. Fukuda, Y.Watanabe, S. Fujii, T. Ozaki, H. Kanaya, S. Shuto, K. Yamakawa, I. Kunishima, T. Hamamoto, and A. Nitayama, "A scalable shield-bitline-overdrive technique for 1.3 V chain FeRAM," in IEEE Int. Solid-State Circuits Conf. Dig., 2010, pp. 262-263.
7. K. Yamaoka, S. Iwanari, Y. Murakuki, H. Hirano, M. Sakagami, T. Nakakuma, T. Miki, and Y. Gohou, "A 0.9 V 1T1C SBT-based embedded non-volatile FeRAM with a reference voltage scheme and multi-layer shielded bit-line structure," in IEEE Int. Solid-State Circuits Conf. Dig., 2004, vol. 1, pp. 50-512.
8. Y. Eslami, A. Sheikholeslami, S. Masui, T. Endo, and S. Kawashima, "A differential-capacitance read scheme for FeRAMs," in Proc. IEEE Symp. VLSI Circuits, 2002, pp. 298-298.
9. S. Kawashima, T. Endo, T. Yamamoto, K. I. Nakabayashi, M. Nakazawa, K. Morita, and M. Aoki, "A bit-line GND sense technique for low-voltage operation FeRAM," in Proc. IEEE Symp. VLSI Circuits, 2001, pp. 127-127.
10. H. P.McAdams,R.Acklin, T. Blake, X.-H.Du, J. Eliason, J. Fong,W. F. Kraus, D. Liu, S. Madan, T. Moise, S. Natarajan, N. Qian, Y. Qiu, K. A.Remack, J.Rodriguez, J. Roscher,A. Seshadri, and S. R. Summerfelt, "A64- MbembeddedFRAMutilizing a 130-nm5LMCu/FSG logic process," IEEE J. Solid-State Circuits, vol. 39, no. 4, pp. 667-677, 2004.
11. I. Stolichnov, A. Tagantsev, N. Setter, J. S. Cross, and M. Tsukada, "Crossover between nucleation-controlled kinetics and domain wall motion kinetics of polarization reversal in ferroelectric films," Appl. Phys. Lett., 2003.
12. A. G. Acosta, J. Rodriguez, B. Obradovic, S. Summerfelt, T. San, K. Green, T. Moise, and S. Krishnan, "Scaling reliability and modeling of ferroelectric capacitors," in Proc. IEEE Int. Reliability Physics Symp., 2010, pp. 689-693.
13. S. R. Summerfelt, T. S. Moise, K. R. Udayakumar, K. Boku, K. Remack, J. Rodriguez, J. Gertas, H. McAdams, S. Madan, J. Eliason, J. Groat, D. Kim, P. Staubs, M. Depner, and R. Bailey, "High-density 8 Mb 1T-1C ferroelectric random access memory embedded within a low-power 130 nm logic process," in Proc. IEEE Int. Symp. Applications of Ferroelectrics, 2007, pp. 9-10.
14. B.-G. Jeon, M.-K. Choi, Y. Song, and K. Kim, "A nonvolatile ferroelectric RAMwith common plate folded bit-line cell and enhanced data sensing scheme," in IEEE Int. Solid-State Circuits Conf. Dig., 2001, vol. 426, pp. 38-39.
15. D. Porat, "Review of sub-nanosecond time-interval measurements," IEEE Trans. Nucl. Sci., vol. 20, no. 5, pp. 36-36, Oct. 1973.
16. H. Tanaka, Y. Nakagome, J. Etoh, E. Yamasaki, M. Aoki, and K. Miyazawa, "Sub-1-dynamic reference voltage generator for battery-operated DRAMs," IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 448-453, 1994.
17. K. N. Leung and P. K. T. Mok, "A CMOS voltage reference based on weighted for CMOS low-dropout linear regulators," IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 146-150, 2003.
18. G. DeVita and G. Iannaccone, "A sub-1-V, 10 ppm/, nanopower voltage reference generator," IEEE J. Solid-State Circuits, vol. 42, no. 7, pp. 1536-1542, 2007.
19. C. Lee, S.-K. Lee, S. Ahn, J. Lee, W. Park, Y. Cho, C. Jang, C. Yang, S. Chung, I.-S. Yun, B. Joo, B. Jeong, J. Kim, J. Kwon, H. Jin, Y. Noh, J. Ha,M. Sung,D.Choi, S. Kim, J. Choi,T. Jeon, H. Park, J.-S. Yang, and Y.-H. Koh, "A 32-Gb MLC NAND flash memory with Vth endurance enhancing schemes in 32 nm CMOS," IEEE J. Solid-State Circuits, vol. 46, no. 1, pp. 97-97, Jan. 2011.
20. C. Villa, D. Vimercati, S. Schippers, S. Polizzi, A. Scavuzzo, M. Perroni, M. Gaibotti, and M. L. Sali, "A 65 nm 1 Gb 2b/cell NOR flash with 2.25 MB/s program throughput and 400 MB/s DDR interface," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 132-132, Jan. 2008.
21. K.-J. Lee, B.-H. Cho, W.-Y. Cho, S. Kang, B.-G. Choi, H.-R. Oh, C.-S. Lee,H.-J. Kim, J.-M. Park, Q.Wang,M.-H. Park,Y.-H. Ro, J.-Y.Choi, K.-S. Kim, Y.-R. Kim, I.-C. Shin, K.-W. Lim, H.-K. Cho, C.-H. Choi, W.-R. Chung, D.-E. Kim, Y.-J. Yoon, K.-S. Yu, G.-T. Jeong, H.-S. Jeong, C.-K. Kwak, C.-H. Kim, and K. Kim, "A 90 nm 1.8 V 512 Mb diode-switch PRAM with 266 MB/s read throughput," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 150-150, Jan. 2008.
22. Y. M. Kang, H. J. Joo, J. H. Park, S. K. Kang, J. H. Kim, S. G. Oh, H. S. Kim, Y. J. Kang, J. Y. Jung, D. Y. Choi, E. S. Lee, S. Y. Lee, H. S. Jeong, and K. Kim, "World smallest 0.34 m COB cell 1T1C 64 Mb FRAM with new sensing architecture and highly reliableMOCVD PZT integration technology," in Proc. IEEE Symp. VLSI Technology, 2006, vol. 0-0, pp. 124-124.
23. T. Sugibayashi, N. Sakimura, T. Honda, K. Nagahara, K. Tsuji, H. Numata, S.Miura, K. Shimura, Y. Kato, S. Saito, Y. Fukumoto,H.Honjo, T. Suzuki, K. Suemitsu, T. Mukai, K. Mori, R. Nebashi, S. Fukami, N. Ohshima, H. Hada, N. Ishiwata, N. Kasai, and S. Tahara, "A 16-Mb toggle MRAM with burst modes," IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2378-2378, Nov. 2007.
24. D. Takashima, Y. Nagadomi, and T. Ozaki, "A 100 MHz ladder FeRAM design with capacitance-coupled-bitline (CCB) cell," in Proc. IEEE Symp. VLSI Circuits, 2010, pp. 227-227.