Model order reduction of large circuits using balanced truncation

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1999-January, Issue , 1999, Pages 237-240

  Rabiei, Payam ^a   Pedram, Massoud ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; CONTROL THEORY; TIMING CIRCUITS;

ARNOLDI ALGORITHM; BALANCED REALIZATIONS; BALANCED TRUNCATION; CIRCUIT-LEVEL SIMULATION; MODEL ORDER REDUCTION; ORIGINAL SYSTEMS; REDUCED ORDER MODELS; REDUCED ORDER SYSTEMS;

CIRCUIT THEORY;

EID: 84872618892     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.1999.760004     Document Type: Conference Paper

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