Offset compensation based on distributed hall cell architecture

IEEE Transactions on Magnetics

Volumn 49, Issue 1, 2013, Pages 105-108

  Kejik, Pavel ^a,b   Bourdelle, Pierre François ^a   Reymond, Serge ^b   Salvi, Fabrice ^c   Farine, Pierre André ^a  

^a EPFL   (Switzerland)

^b Sensima Technology SA   (Switzerland)

^c PregLem SA   (Switzerland)

Author keywords

CMOS; Hall device; noise; offset; spinning current technique

Indexed keywords

CMOS; HALL DEVICES; NOISE; OFFSET; SPINNING CURRENT;

ELECTRICAL ENGINEERING; MAGNETIC MATERIALS;

HALL EFFECT DEVICES;

EID: 84871823501     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMAG.2012.2219615     Document Type: Article

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