Energy savings via dead sub-block prediction

Proceedings - Symposium on Computer Architecture and High Performance Computing

Volumn , Issue , 2012, Pages 51-58

  Alves, Marco A Z ^a   Khubaib, ^b   Ebrahimi, Eiman ^c   Narasiman, Veynu T ^b   Villavieja, Carlos ^b   Navaux, Philippe O A ^a   Patt, Yale N ^b  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b The University of Texas at Austin   (United States)

^c NVIDIA   (United States)

Author keywords

Cache Memory; Dead Line Predictor; Dead Sub Block Predictor; Energy Savings

Indexed keywords

CACHE HIERARCHIES; DEAD LINE PREDICTOR; ENERGY REDUCTION; ENERGY WASTES; REPLACEMENT POLICY; SPATIAL LOCALITY; SUB-BLOCKS;

BUFFER STORAGE; COMPUTER ARCHITECTURE; ENERGY CONSERVATION;

CACHE MEMORY;

EID: 84871651935     PISSN: 15506533     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SBAC-PAD.2012.30     Document Type: Conference Paper

References (16)

1. S. Li et al., "Mcpat: an integrated power, area, and timing modeling framework for multicore and manycore architectures," in IEEE/ACM Int. Symp. on Microarchitecture, 2009, pp. 469-480.
2. S. Kaxiras et al., "Cache decay: exploiting generational behavior to reduce cache leakage power," in IEEE/ACM Int. Symp. on Computer Architecture, 2001, pp. 240-251.
3. S. Kumar et al., "Exploiting spatial locality in data caches using spatial footprints," in ACM SIGARCH Computer Architecture News, vol. 26, no. 3, 1998, pp. 357-368.
4. C. F. Chen et al., "Accurate and complexity-effective spatial pattern prediction," in IEEE Int. Symp. on High Performance Computer Architecture, 2004, pp. 276-287.
5. M. Kharbutil et al., "Counter-based cache replacement and bypassing algorithms," IEEE Transactions on Computers, vol. 57, no. 4, pp. 433-447, 2008.
6. J. Abella et al., "Iatac: a smart predictor to turn-off 1 2 cache lines," ACM Transactions on Architecture and Code Optimization, vol. 2, no. 1, pp. 55-77, 2005.
7. H. Jin et al., "The openmp implementation of nas parallel benchmarks and its performance," in Technical Report: NAS-99-011, 1999.
8. DD: a circuit technique to reduce leakage in deep-submicron cache memories," in ACM Int. Symp. on Low Power Electronics and Design, 2000, pp. 90-95.
9. I. S. P. Division, "System/370 model 155 theory of operation/diagrams manual (volume 5)," 1974.
10. P. Pujara et al., "Cache noise prediction," IEEE Transactions on Computers, vol. 57, no. 10, pp. 1372-1386, 2008.
11. A.-C. Lai et al., "Selective, accurate, and timely self-invalidation using last-touch prediction," in IEEE/ACM Int. Symp. on Computer Architecture, 2000, pp. 139-148.
12. A. C. Lai et al., "Dead-block prediction & dead-block correlating prefetchers," in IEEE/ACM Int. Symp. on Computer Architecture, 2001, pp. 144-154.
13. S. Khan et al., "Using dead blocks as a virtual victim cache," in IEEE/ACM Int. Conference on Parallel Architectures and Compilation Techniques, 2010, pp. 489-500.
14. H. Patil et al., "Pinpointing representative portions of large intel itanium programs with dynamic instrumentation," in IEEE/ACM Int. Symp. on Microarchitecture, 2004, pp. 81-92.
15. N. Muralimanohar et al., "Architecting efficient interconnects for large caches with cacti 6.0," IEEE Micro, vol. 28, no. 1, pp. 69-79, 2008.
16. Y. Liu et al., "Accurate temperature-dependent integrated circuit leakage power estimation is easy," in Design, Automation and Test in Europe, 2007, pp. 1526-1531.