Enabling high-performance crossbars through a floorplan-aware design

Proceedings of the International Conference on Parallel Processing

Volumn , Issue , 2012, Pages 269-278

  Roca, Antoni ^a   Hernández, Carles ^a   Flich, José ^a   Silla, Federico ^a   Duato, José ^a  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

Author keywords

crossbar; network implementation; Network on Chip

Indexed keywords

CHIP MULTIPROCESSORS; CROSSBAR; HIGH RADIX; LOW LATENCY; MESSAGE LATENCY; MULTI-PROCESSORS; NETWORK DIAMETER; NETWORK LATENCIES; NETWORK ON CHIP; NETWORK THROUGHPUT; NETWORKS ON CHIPS; NOC ARCHITECTURES; OPERATING FREQUENCY; PHYSICAL MAPPING; PLANAR TOPOLOGY; QUEUING DELAY; SYSTEM ON CHIPS; SYSTEM SIZE; WIRE LENGTH;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; THROUGHPUT; VLSI CIRCUITS; WIRE;

NETWORK ARCHITECTURE;

EID: 84871129420     PISSN: 01903918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICPP.2012.24     Document Type: Conference Paper

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