A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance

European Solid-State Circuits Conference

Volumn , Issue , 2012, Pages 313-316

  Clerc, Sylvain ^a   Abouzeid, Fady ^a   Gasiot, Gilles ^a   Gauthier, David ^b   Roche, Philippe ^a  

^a STMICROELECTRONICS   (France)

^b EASii IC   (France)

Author keywords

[No Author keywords available]

Indexed keywords

BIT-INTERLEAVING; BITCELL; ENERGY ACCESS; ENERGY GAIN; ERROR CORRECTING CODE; MULTI-BIT ERROR; OPERATING VOLTAGE; SOFT ERROR RATE; SOFT-ERROR TOLERANCE; TERRESTRIAL RADIATION; ULTRA-LOW-VOLTAGE; VOLTAGE RANGES; WAFER LEVEL;

ERROR CORRECTION; INFRARED RADIATION;

STATIC RANDOM ACCESS STORAGE;

EID: 84870850740     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2012.6341317     Document Type: Conference Paper

References (14)

1. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, "Leakage current mechanisms and leakage reduction techniques in deepsubmicrometer cmos circuits," Proceedings of the IEEE, vol. 91, no. 2, pp. 305-327, Feb. 2003.
2. H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye, "Alpha- particleinduced soft errors and multiple cell upsets in 65-nm 10t subthreshold sram," in Reliability Physics Symposium (IRPS), 2010 IEEE International, May 2010, pp. 213-217.
3. N. Verma and A. Chandrakasan, "A 65nm 8t sub-vt sram employing sense-amplifier redundancy," in Solid-State Circuits Conference, 2007. ISSCC 2007. Digest of Technical Papers. IEEE International, 2007, pp. 328-606.
4. J. Kulkarni and K. Roy, "Ultralow-voltage process-variation-tolerant schmitt-trigger-based sram design," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 20, no. 2, pp. 319-332, feb. 2012.
5. D. Kim, G. Chen, M. Fojtik, M. Seok, D. Blaauw, and D. Sylvester, "A 1.85fw/bit ultra low leakage 10t sram with speed compensation scheme," in Circuits and Systems (ISCAS), 2011 IEEE International Symposium on, may 2011, pp. 69-72.
6. I. J. Chang, J.-J. Kim, S. Park, and K. Roy, "A 32kb 10t subthreshold sram array with bit-interleaving and differential read scheme in 90nm cmos," in Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International, 2008, pp. 388-622.
7. E. Seevinck, F. List, and J. Lohstroh, "Static-noise margin analysis of mos sram cells," Solid-State Circuits, IEEE Journal of, vol. 22, no. 5, pp. 748-754, Oct. 1987.
8. F. Abouzeid, "Subthreshold architecture and digital circuits study in submicronic cmos technology," Ph.D. dissertation, 2010.
9. M. Sharifkhani and M. Sachdev, "Sram cell stability: A dynamic perspective," Solid-State Circuits, IEEE Journal of, vol. 44, no. 2, pp. 609-619, 2009.
10. EASii-IC. [Online]. Available: Http://www.easii-ic.com/
11. Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices, JEDEC Std., 2006. [Online]. Available: Http://www.jedec.org/standardsdocuments/ results/JESD89/
12. M. Nicolaidis, Ed., Soft Errors on Modern Electronics Systems. Springer, 2011.
13. B. Rooseleer, S. Cosemans, and W. Dehaene, "A 65 nm, 850 mhz, 256 kbit, 4.3 pj/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link," in ESSCIRC (ESSCIRC), 2011 Proceedings of the, sept. 2011, pp. 519-522.
14. M. Sinangil, N. Verma, and A. Chandrakasan, "A reconfigurable 65nm sram achieving voltage scalability from 0.2 to 1.2v and performance scalability from 20khz to 200mhz," in Solid-State Circuits Conference, 2008. ESSCIRC 2008. 34th European, sept. 2008, pp. 282-285.