Advancing high performance heterogeneous integration through die stacking

European Solid-State Circuits Conference

Volumn , Issue , 2012, Pages 18-24

  Madden, Liam ^a   Wu, Ephrem ^a   Kim, Namhoon ^a   Banijamali, Bahareh ^a   Abugharbieh, Khaldoon ^a   Ramalingam, Suresh ^a   Wu, Xin ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; CHANNEL CHARACTERISTICS; COPLANARITY; DIE STACKING; ELECTRICAL SIMULATION; ELECTRONIC DESIGN AUTOMATION; HETEROGENEOUS INTEGRATION; HIGH BANDWIDTH; LOW-K DIELECTRIC MATERIALS; LOW-TEMPERATURE CO-FIRED CERAMICS; MICRO-BUMPS; MODELING AND ANALYSIS; MONOLITHIC SOLUTIONS; MULTI-CHIP; OPTIMAL SIGNALS; PACKAGE RELIABILITY; PACKAGE SUBSTRATES; TEST CHIPS; THROUGH SILICON VIAS; TIMING VERIFICATION;

BANDWIDTH; CERAMIC PRODUCTS; DIELECTRIC MATERIALS; OPTIMIZATION; RELIABILITY ANALYSIS; SILICON; THREE DIMENSIONAL COMPUTER GRAPHICS; TRANSCEIVERS;

INTEGRATION;

EID: 84870807894     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ESSCIRC.2012.6341246     Document Type: Conference Paper

References (5)

1. Xilinx, Inc., "7 Series FPGAs Overview," http://www.xilinx.com/ support/documentation/data-sheets/ds180-7Seri es-Overview.pdf, May 5, 2012.
2. The CFP MSA, "CFP MSA 100G Roadmap and Applications," http://www.cfp-msa.org/Documents/CFP-MSA-roadmap.pdf, November 2010.
3. The Interlaken Alliance, "Interlaken Protocol Specification, v1.2," http://www.interlakenalliance.com/Interlaken-Protocol-Definition-v1. 2.pdf, October 2008.
4. Agilent Application Note, "Ultra-low Impedance Measurements Using 2-port Measurement"
5. http://www.xilinx.com/power