A novel floating-point function unit combining MAF and 3-input adder

2012 IEEE International Conference on Signal Processing, Communications and Computing, ICSPCC 2012

Volumn , Issue , 2012, Pages 109-113

  Yao, Tao ^a   Gao, Deyuan ^a   Ren, Xianglong ^a   Han, Limin ^a   Fan, Xiaoya ^a   Yang, Lei ^b  

^a NORTHWESTERN POLYTECHNICAL UNIVERSITY   (China)

^b SHANDONG AGRICULTURAL UNIVERSITY   (China)

Author keywords

3 input FP adder; FP function unit; Mulitply add fused; once rounding operation

Indexed keywords

ATTRACTIVE SOLUTIONS; CMOS TECHNOLOGY; EXHAUSTIVE TESTING; FLOATING POINT UNITS; FLOATING-POINT FUNCTIONS; FUNCTION UNIT; MULITPLY-ADD-FUSED; MULTIINPUT; PROPOSED ARCHITECTURES; ROUNDING OPERATION; SMALL DATA; STREAM PROCESSOR;

CMOS INTEGRATED CIRCUITS; SIGNAL PROCESSING;

DIGITAL ARITHMETIC;

EID: 84869778120     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICSPCC.2012.6335714     Document Type: Conference Paper

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