Designing with partially depleted SOI

Proceedings of the IEEE 2nd Dallas CAS Workshop on Low Power/Low Voltage Mixed-Signal Circuits and Systems, DCAS 2001

Volumn , Issue , 2001, Pages P31-P34

  Mogul, H ^a   Marshall, A ^a   Natarajan, S ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; ELECTRIC SIGNAL SYSTEMS; INTEGRATED CIRCUITS; LOW POWER ELECTRONICS; RECONFIGURABLE HARDWARE;

BODY-TIES; CIRCUIT PERFORMANCE; MEMORY APPLICATIONS; PARTIALLY DEPLETED SOI; SIMPLE CIRCUITS;

MIXED SIGNAL INTEGRATED CIRCUITS;

EID: 84869679157     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DCAS.2001.920989     Document Type: Conference Paper

References (3)

1. A. Marshall & S. Natarajan, "SOI Design", Kluwer Academic Publishing, To be published.
2. P.R. Gray & R. G. Meyer, "Analysis and Design of Analog Integrated Circuits, John Wiley & Sons, Inc. 1993.
3. B.Prince, "Semiconductor Memories", John Wiley & Sons