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Volumn , Issue , 2012, Pages

Reconfigurable sleep transistor for GIDL reduction in ultra-low standby power systems

Author keywords

[No Author keywords available]

Indexed keywords

ACTIVE MODE; AREA PENALTY; BATTERY LIFE; BATTERY VOLTAGES; BODY CONTACTS; CMOS TEST CHIP; LEAKAGE MECHANISM; POWER GATINGS; SLEEP MODE; SLEEP TRANSISTORS; STAND-BY LEAKAGE; STANDBY POWER; SUB-THRESHOLD LEAKAGE; VOLUME REDUCTIONS;

EID: 84869381376     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2012.6330628     Document Type: Conference Paper
Times cited : (6)

References (11)
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  • 4
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    • Feb.
    • G. Chen, et al., "A Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor," ISSCC Dig. Tech. Papers, pp. 310-311, Feb. 2011.
    • (2011) ISSCC Dig. Tech. Papers , pp. 310-311
    • Chen, G.1
  • 5
    • 84855652495 scopus 로고    scopus 로고
    • Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial
    • (invited), Jan.
    • M. Alioto, "Ultra-Low Power VLSI Circuit Design Demystified and Explained: A Tutorial," IEEE Trans. on Circuits and Systems - part I (invited), vol. 59, no. 1, pp. 3-29, Jan. 2012.
    • (2012) IEEE Trans. on Circuits and Systems - Part I , vol.59 , Issue.1 , pp. 3-29
    • Alioto, M.1
  • 7
    • 0031635212 scopus 로고    scopus 로고
    • A New Technique for Standby Leakage Reduction in High-Performance Circuits
    • Y. Ye, S. Borkar, V. De, "A New Technique for Standby Leakage Reduction in High-Performance Circuits," IEEE Symp. VLSI Circuits Dig., June 1998, pp. 40-41.
    • IEEE Symp. VLSI Circuits Dig., June 1998 , pp. 40-41
    • Ye, Y.1    Borkar, S.2    De, V.3
  • 9
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    • Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors
    • Nov.
    • J. W. Tschnz, et al., "Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors," IEEE J. Solid-State Circuits, vol. 38, no. 11, Nov. 2003, pp. 1838-1845.
    • (2003) IEEE J. Solid-State Circuits , vol.38 , Issue.11 , pp. 1838-1845
    • Tschnz, J.W.1
  • 10
    • 1542605495 scopus 로고    scopus 로고
    • Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-μm CMOS
    • Feb.
    • S. Narenda, et al., "Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-μm CMOS," IEEE J. Solid-State Circuits, vol. 39, no. 2, Feb. 2004, pp. 501-510.
    • (2004) IEEE J. Solid-State Circuits , vol.39 , Issue.2 , pp. 501-510
    • Narenda, S.1
  • 11
    • 84870652518 scopus 로고    scopus 로고
    • BSIM4 MOSFET model manual, http://www-device.eecs.berkeley.edu/bsim/ Files/BSIM4/BSIM470/BSIM470-Manual.pdf
    • BSIM4 MOSFET Model Manual


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.