Seamless integration of parallelism and memory hierarchy

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 2380 LNCS, Issue , 2002, Pages 856-867

  Fantozzi, Carlo ^a   Pietracaprina, Andrea ^a   Pucci, Geppino ^a  

^a UNIVERSITY OF PADOVA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATA THEORY;

COMMUNICATION LOCALITY; HIERARCHICAL STRUCTURES; MEMORY HIERARCHY; PARALLEL MACHINE; SEAMLESS INTEGRATION; SEQUENTIAL ALGORITHM; SIMULATION STRATEGIES; TEMPORAL LOCALITY;

PARALLEL PROCESSING SYSTEMS;

EID: 84869155286     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-45465-9_73     Document Type: Conference Paper

References (17)

1. Valiant, L.G.: A bridging model for parallel computation. Communications of the ACM 33 (1990) 103-111
2. Dehne, F., Fabri, A., Rau-Chaplin, A.: Scalable parallel geometric algorithms for coarse grained multicomputers. International Journal on Computational Geometry 6 (1996) 379-400
3. Brent, R.P.: The parallel evaluation of general arithmetic expressions. Journal of the ACM 21 (1974) 201-206
4. Vitter, J.S., Shriver, E.A.M.: Algorithms for parallel memory II: Hierarchical multilevel memories. Algorithmica 12 (1994) 148-169
5. Aggarwal, A., Alpern, B., Chandra, A.K., Snir, M.: A model for hierarchical memory. In: Proc. of the 19th ACM STOC. (1987) 305-314
6. Alpern, B., Carter, L., Ferrante, J.: Modeling parallel computers as memory hierarchies. In Programming Models for Massively Parallel Computers. IEEE Computer Society Press (1993) 116-123
7. Heywood, T., Ranka, S.: A practical hierarchical model of parallel computation. I. the model. Journal of Parallel and Distributed Computing 16 (1992) 212-232
8. Bilardi, G., Preparata, F.P.: Processor-time tradeoffs under bounded-speed message propagation: Part I, upper bounds. Theory of Computing Systems 30 (1997) 523-546
9. Bilardi, G., Preparata, F.P.: Processor-time tradeoffs under bounded-speed message propagation: Part II, lower bounds. Theory of Computing Systems 32 (1999) 531-559
10. Dehne, F., Dittrich,W., Hutchinson, D.: Efficient external memory algorithms by simulating coarse-grained parallel algorithms. In: Proc. of the 9th ACM SPAA. (1997) 106-115
11. Dehne, F., Dittrich, W., Hutchinson, D., Maheshwari, A.: Reducing I/O complexity by simulating coarse grained parallel algorithms. In: Proc. of the 13th IPPS. (1999) 14-20
12. Sibeyn, J., Kaufmann, M.: BSP-like external-memory computation. In: Proc. of the 3rd Italian Conference on Algorithms and Complexity. LNCS 1203 (1997) 229-240
13. De la Torre, P., Kruskal, C.P.: Submachine locality in the bulk synchronous setting. In: Proc. of EUROPAR 96. LNCS 1124 (1996) 352-358
14. Bilardi, G., Peserico, E.: A characterization of temporal locality and its portability across memory hierarchies. In: Proc. of ICALP 2001. LNCS 2076 (2001) 128-139
15. Bilardi, G., Pietracaprina, A., Pucci, G.: Aquantitative measure of portability with application to bandwidth-latency models for parallel computing. In: Proc. of EUROPAR 99. LNCS 1685 (1999) 543-551
16. Fantozzi, C., Pietracaprina, A., Pucci, G.: Implementing shared memory on clustered machines. In: Proc. of IPDPS 2001. (2001)
17. Bilardi, G., Fantozzi, C., Pietracaprina, A., Pucci, G.: On the effectiveness of D-BSP as a bridging model of parallel computation. In: Proc. of ICCS 2001. LNCS 2074 (2001) 579-588