Making write less blocking for read accesses in phase change memory

Proceedings of the 2012 IEEE 20th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, MASCOTS 2012

Volumn , Issue , 2012, Pages 269-277

  Yue, Jianhui ^a   Zhu, Yifeng ^a  

^a UNIVERSITY OF MAINE   (United States)

Author keywords

computer architecture; phase change memory; read latency

Indexed keywords

BIT DENSITY; CHIP-LEVEL; FAST READ; MEMORY ACCESS; MEMORY LATENCIES; MICRO ARCHITECTURES; MULTI-CORE PROCESSOR; NONVOLATILITY; PHASE CHANGES; READ LATENCY; REAL SYSTEMS; SIMULATION EXPERIMENTS; SPATIAL LOCALITY; WRITE SPEED;

COMPUTER ARCHITECTURE; DYNAMIC RANDOM ACCESS STORAGE; MEMORY ARCHITECTURE; PHASE CHANGE MEMORY; TELECOMMUNICATION SYSTEMS;

COMPUTER SIMULATION;

EID: 84868241935     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MASCOTS.2012.39     Document Type: Conference Paper

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