Dynamic last-level cache allocation to reduce area and power overhead in directory coherence protocols

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 7484 LNCS, Issue , 2012, Pages 206-218

  Lodde, Mario ^a   Flich, Jose ^a   Acacio, Manuel E ^b  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

^b UNIVERSITY OF MURCIA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

AREA SAVINGS; ASSOCIATIVITY; CACHE ALLOCATION; CHIP AREAS; CHIP MULTIPROCESSOR; COHERENCE PROTOCOL; DIRECTORY STRUCTURE; EVALUATION RESULTS; EXECUTION TIME; LEAKAGE ENERGIES; MEMORY HIERARCHY; OFF-CHIP; ON CHIP MEMORY; POWER OVERHEAD; PRIVATE DATA; STATIC POWER; TILED CMP;

ARTIFICIAL INTELLIGENCE;

EID: 84867643144     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-32820-6_22     Document Type: Conference Paper

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